> Anyone help? > > I'm working in academia and need to build a 300-receiver channel > single-bit digitiser / cross-correlator with a single frequency channel > having a bandwidth of 300 MHz, centre frequency ~3 GHz. The single bit > digitisers sample I&Q giving a total data rate of 180 Gbps and using XOR > gates to do the cross-correlations, the total computation rate is 54 T XOR > operations per second. I need to accumulate cross-correlations typically > for times ranging from 10 ms to a few seconds. The system would comprise > an array of single bit digitisers linked via a high speed data bus to FPGA > boards for the cross-correlation/accumulation. I've no skills in board > design but could probably learn VHDL. I don't have funding to commission a > design and build but wondered if anyone in this community could advise how > I should go about building this system at our university.
Hi Neal. I think the main problem you face is the I/O. I'm assuming your sample rate is 300 ms/s? Clocking the FPGA at 300 MHz is pushing it, but not completely insane. The 180 Gbps is above the capacity of the Roach-2, but maybe R-3 can do it. There are other off the shelf hardware platforms you could look at, like pico computing that might have enough I/O. Dumping the output at 10 ms shouldn't be a problem, as that's only 3.6 Mbps at a 4 bit width, or ~29 Mbps at 32 bits wide. Do you already have the digitizers? That's probably a nice bit of engineering in itself. There has been some work on using the Xilinx I/O block bits as single-bit ADCs. I don't remember the details. John > > Thank you for any help you can provide. > > Neil > "Before acting on this email or opening any attachments you should read > the Manchester Metropolitan University email disclaimer available on its > website http://www.mmu.ac.uk/emaildisclaimer " >
