I believe that each ZDOK is good for about 50 Gb/s. A ROACH2 has two ZDOK ports. Presumably you'll give up a pin or two for clocks so maybe 40Gb/s is a more realistic rate. We use an ADC that achieves 40Gb/s over 32 of the 40 ZDOK pin pairs. . But you'll also have to physically interface the digitizers, so whether you can have multiple digitizers time multiplexed on the same FPGA pins or whether you need one pin (pair?) per digitizer might also be limiting.
Jack On Fri, 18 Dec 2015 at 16:46 Neil Salmon <[email protected]> wrote: > Jack, > > Thanks for help. Do you have any idea of the I/O capacity of a single > Roach2 board – just trying to figure out how many I may need? > > Thank you, > > Neil > > > > *From:* Jack Hickish [mailto:[email protected]] > *Sent:* 18 December 2015 15:08 > *To:* James Smith; Neil Salmon > > > *Cc:* [email protected] > *Subject:* Re: [casper] building 300-receiver channel cross-correlator > > > > Hi Neil, > > > > A bit more information would be useful, but it sounds like if you could > construct a ZDOK card that interfaced some (40, one per differential pair?) > of your digitizers to a ROACH board you could use a handful of ROACH boards > to perform all of the cross multiplication and accumulation and interface > with CPU data recorders / post-processors. > > > > Jack > > > > On Fri, 18 Dec 2015 at 14:26 James Smith <[email protected]> wrote: > > Hello Neil, > > > > CASPER tools could probably do what you're looking for, but I found your > description a bit confusing. You're going to need to clarify somewhat. > > > > Regards, > > James > > > > > > On Fri, Dec 18, 2015 at 4:15 PM, Neil Salmon <[email protected]> wrote: > > Anyone help? > > > > I’m working in academia and need to build a 300-receiver channel > single-bit digitiser / cross-correlator with a single frequency channel > having a bandwidth of 300 MHz, centre frequency ~3 GHz. The single bit > digitisers sample I&Q giving a total data rate of 180 Gbps and using XOR > gates to do the cross-correlations, the total computation rate is 54 T XOR > operations per second. I need to accumulate cross-correlations typically > for times ranging from 10 ms to a few seconds. The system would comprise an > array of single bit digitisers linked via a high speed data bus to FPGA > boards for the cross-correlation/accumulation. I’ve no skills in board > design but could probably learn VHDL. I don’t have funding to commission a > design and build but wondered if anyone in this community could advise how > I should go about building this system at our university. > > > > Thank you for any help you can provide. > > > > Neil > > "Before acting on this email or opening any attachments you should read > the Manchester Metropolitan University email disclaimer available on its > website http://www.mmu.ac.uk/emaildisclaimer " > > > > "Before acting on this email or opening any attachments you should read > the Manchester Metropolitan University email disclaimer available on its > website http://www.mmu.ac.uk/emaildisclaimer " >
