On 05/25/2018 12:04 PM, Michael Inggs wrote:
Hi Dan
One of the tradeoff studies the guys are doing is the cost of a 48
channel analogue downconverter and low sample rate ADC. At present,
direct demod with a SNAP looks simpler in terms of hardware
complexity, but has not been costed.
One of the team has actually implemented all the digital backend
(including RFI excision) on a GPU, so in principle, all we need are
time stamped packets of samples, and nothing on the FPGA, except
demod, decimation.
Thanks for the ideas coming in to the team.
Regards
So, here's a wee "out there" suggestion.
The RTLSDR can be used in a direct-sample mode, bypassing the hideous
phase offset problems with the R820T2 tuner chip.
Build up a converter array that has a single LO that can down-convert
all antenna inputs to 10.7MHz, which can be direct-sampled by
the RTLSDR, which you can common-clock with a low-phase-noise master
clock at 28.8MHz.
There are a plethora of IF filters available, very, very cheaply at
10.7Mhz, and because they're designed largely for the FM radio band, have
bandwidths that closely match your requirements. In terms of RF filters:
http://www.microsaw.fi/pdf/saw-filter/327-mhz/M075-327_8M2.pdf
Your residual problems would be:
o algorithms to time-synchronize the inputs from all the RTLSDRs
Injecting a coded test-tone has been used by me for doing this
o figuring out if you can have so many USB devices on a single
computer system
The problem with finding a low-speed ADC that *also* has wide analog
bandwidth is that they largely don't exist as far as I can tell, so you end
up going for a *much* faster ADC, and under-clocking it, and this is
expensive.
I can't remember whether Haystack used a down-conversion approach or not.
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