Thanks for that fix,Adam.
I understand what I did wrong on 2,3 and 4. I am still unclear on 1. I will
dig deeper to see what I did there to break it.
The compilation went through and I generated the fpg file, but when I run
the python code, I get an error in the line where it is uploading the fpg
file to the ram and programming. I am not sure what error this is
corresponding to. I ran the python file line by line as well in the
terminal and also see the same error. I downloaded the py file from github.
>From what I can understand, there is no need to change anything in here.
Connecting to Red Pitaya: rp-F07516.local
Uploading:
/home/cet/RP_work/models/rp_tut3/tut_spec_adam/outputs/tut_spec_adam_2020-04-14_1158.fpg
Traceback (most recent call last):
File "tut_spec.py", line 23, in <module>
fpga.upload_to_ram_and_program(file_fpg)
File "build/bdist.linux-x86_64/egg/casperfpga/casperfpga.py", line 319,
in upload_to_ram_and_program
File "build/bdist.linux-x86_64/egg/casperfpga/casperfpga.py", line 747,
in get_system_information
File "build/bdist.linux-x86_64/egg/casperfpga/casperfpga.py", line 588,
in _create_memory_devices
File "build/bdist.linux-x86_64/egg/casperfpga/snap.py", line 59, in
from_device_info
RuntimeError: accum0_snap_ss has mask length_bytes 32768 bytes, but mem map
length_bytes 16384 bytes
On Tue, Apr 14, 2020 at 3:12 AM Adam Isaacson <aisaac...@ska.ac.za> wrote:
> Hi Aravind,
>
> I have found the following issues:
>
> 1) The ADC yellow block was modified and the link to the library was
> broken. This meant that the number of bits parameter did not propagate down
> to the cast blocks and so they were still set at 10 bits. I see you added
> some simulation blocks, but probably broke the links in the process.
>
> 2) The constant xilinx blocks for the imaginary inputs to the FFT were set
> at 10 bits and not 14 bits.
>
> 3) The accumdat_snap snapshot had the incorrect number of bits for the
> "in_Ch_acc". This should not have been modified, as it is not influenced by
> the ADC number of bits.
>
> 4) I fixed the bit growth through your system - hopefully this is correct
> now.
>
> Please see attached modified version. It should compile now.
>
> Kind regards,
>
> Adam Isaacson
> South African Radio Astronomy Observatory (SARAO)
> Hardware Manager
> Cell: (+27) 825639602
> Tel: (+27) 215067300
> email: aisaac...@ska.ac.za
>
>
>
> On Mon, Apr 13, 2020 at 10:49 PM Aravind Venkitasubramony <
> aravind.venkitasubram...@colorado.edu> wrote:
>
>> Hi Adam
>>
>> I revisited the spectrometer tutorial after finishing the second
>> tutorial. I have attached the slx file along with. I have modified
>> everything I could understand but I still get the following error while
>> compiling
>>
>> The input type propagated to this block did not match the specified type.
>> Expected Type: Fix_14_0
>> Actual Type: Fix_10_0
>>
>> It would be great if you could take a look and tell me what I am doing
>> wrong.
>>
>> On Tue, Apr 7, 2020 at 2:22 AM Adam Isaacson <aisaac...@ska.ac.za> wrote:
>>
>>> Dear Aravind,
>>>
>>> You can do any tutorial in any order, but as a beginner it is better to
>>> do it in order. The spectrometer tutorial should be able to work for a 14
>>> bit board, but if you go through the steps you will see that the
>>> spectrometer bit growth is based on an input of 10 bits. You would need to
>>> change that based on an input of 14 bits. The python script would also need
>>> to be updated to handle 14 bits or so I think. This could be why you are
>>> experiencing these issues reading back from the snapshots.
>>>
>>> I would have to see your script and your slx file that you have updated
>>> in order to see if they are correct. Send that to me and I will glance over
>>> it.
>>>
>>> Kind regards,
>>>
>>> Adam Isaacson
>>> South African Radio Astronomy Observatory (SARAO)
>>> Hardware Manager
>>> Cell: (+27) 825639602
>>> Tel: (+27) 215067300
>>> email: aisaac...@ska.ac.za
>>>
>>>
>>>
>>> On Tue, Apr 7, 2020 at 1:04 AM Aravind Venkitasubramony <
>>> arve9...@colorado.edu> wrote:
>>>
>>>> I guess I have to complete the tutorial 2 first before jumping on the
>>>> third one to get an answer why. I will see if that helps.
>>>>
>>>> On Monday, April 6, 2020 at 4:35:34 PM UTC-6, Aravind Venkitasubramony
>>>> wrote:
>>>>>
>>>>> Sorry for the confusion. I meant the wide(ish) spectrometer tutorial 3
>>>>>
>>>>> On Monday, April 6, 2020 at 3:58:50 PM UTC-6, Aravind Venkitasubramony
>>>>> wrote:
>>>>>>
>>>>>> Does the spectrometer tutorial work with the 14 bit Red Pitaya board
>>>>>> as well? The tutorial mentions the 10 bit board, but I am using the 14
>>>>>> bit
>>>>>> board version.
>>>>>>
>>>>>> Also, going through the spectrometer tutorial with the 14 bit board,
>>>>>> I get the following message at the terminal when executing the python
>>>>>> command. Can someone help me with what might be the issue here?
>>>>>>
>>>>>> Connecting to Red Pitaya: rp-F07516.local
>>>>>> Uploading: tut_spec.fpg
>>>>>> These are the devices in your design ...
>>>>>> ['acc_cnt', 'acc_len', 'accum0_snap_ss_bram', 'accum0_snap_ss_ctrl',
>>>>>> 'accum0_snap_ss_status', 'accum1_snap_ss_bram', 'accum1_snap_ss_ctrl',
>>>>>> 'accum1_snap_ss_status', 'accumdat_snap_ss_bram',
>>>>>> 'accumdat_snap_ss_ctrl',
>>>>>> 'accumdat_snap_ss_status', 'adc_dv', 'adc_sample_cnt',
>>>>>> 'adc_voltage_snap_ss_bram', 'adc_voltage_snap_ss_ctrl',
>>>>>> 'adc_voltage_snap_ss_status', 'fft_sync_inc0', 'fft_sync_inc1',
>>>>>> 'reg_cntrl', 'snap_gap', 'sync_cnt', 'sync_reg', 'sys_block',
>>>>>> 'sys_board_id', 'sys_clkcounter', 'sys_rev', 'sys_rev_rcs',
>>>>>> 'sys_scratchpad']
>>>>>> Traceback (most recent call last):
>>>>>> File "tut_spec.py", line 38, in <module>
>>>>>> spec0=fpga.snapshots.accum0_snap_ss.read(arm=False)['data']
>>>>>> File "/usr/local/lib/python2.7/dist-packages/casperfpga/snap.py",
>>>>>> line 227, in read
>>>>>> rawdata, rawtime = self.read_raw(**kwargs)
>>>>>> File "/usr/local/lib/python2.7/dist-packages/casperfpga/snap.py",
>>>>>> line 333, in read_raw
>>>>>> bram_dmp['length'] / (self.width_bits / 8)))
>>>>>> RuntimeError: accum0_snap_ss.read_uint() - expected 16384 bytes, got
>>>>>> 32
>>>>>>
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>>>>
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import casperfpga
import matplotlib
import matplotlib.pyplot as plt
import numpy as np
import argparse
import time
parser = argparse.ArgumentParser()
parser.add_argument("-f", "--file", help="fpg file to upload to red-pitaya")
parser.add_argument("-r", "--redpitaya", help="Red-Pitaya hostname or IP address")
parser.add_argument("-a", "--accums", help="Number of accumulations",default=4)
args = parser.parse_args()
red_pitaya = args.redpitaya
print("Connecting to Red Pitaya: {0}".format(red_pitaya))
fpga=casperfpga.CasperFpga(red_pitaya)
file_fpg=args.file
print("Uploading: {0}".format(file_fpg))
fpga.upload_to_ram_and_program(file_fpg)
fft_len=256
acc_len=int(args.accums)
snap_cyc=10
print("These are the devices in your design ...")
print(fpga.listdev())
fpga.write_int('acc_len',acc_len)
fpga.write_int('snap_gap',snap_cyc)
fpga.write_int('reg_cntrl',1)
time.sleep(5)
fpga.snapshots.accum0_snap_ss.arm()
spec0=fpga.snapshots.accum0_snap_ss.read(arm=False)['data']
fpga.snapshots.accum1_snap_ss.arm()
spec1=fpga.snapshots.accum1_snap_ss.read(arm=False)['data']
fpga.snapshots.accumdat_snap_ss.arm()
spec_dat=fpga.snapshots.accumdat_snap_ss.read(arm=False)['data']
fig0, ax0= plt.subplots()
ax0.plot(np.array(spec0['val_acc0'][0:2*acc_len*fft_len]).astype(float)*5e7,'r-.')
ax0.plot(spec0['P_acc0'][0:2*acc_len*fft_len],'b-')
ax0.set(xlabel='channel',ylabel='power',title='Ch0')
ax0.set_xlim(0,2*acc_len*fft_len)
fig1, ax1= plt.subplots()
ax1.plot(np.array(spec1['val_acc1'][0:2*acc_len*fft_len]).astype(float)*5e7,'r-.')
ax1.plot(spec1['P_acc1'][0:2*acc_len*fft_len],'b-')
ax1.set(xlabel='channel',ylabel='power',title='Ch1')
ax1.set_xlim(0,2*acc_len*fft_len)
fig2, ax2= plt.subplots()
valid = np.array(spec0['val_acc0'][0:2*acc_len*fft_len]).astype(bool)
spectrum0 = np.array(spec0['P_acc0'][0:2*acc_len*fft_len])
spectrum0 = np.fft.fftshift(spectrum0[:256])
ax2.plot(np.linspace(-256/2,256/2-1,256)*125/256,spectrum0[:256].astype(float),'b-')
ax2.set(xlabel='freq (MHz)',ylabel='power',title='Ch0')
ax2.set_xlim(0,50)
fig3, ax3= plt.subplots()
valid = np.array(spec1['val_acc1'][0:2*acc_len*fft_len]).astype(bool)
spectrum1 = np.array(spec1['P_acc1'][0:2*acc_len*fft_len])
spectrum1 = np.fft.fftshift(spectrum1[:256])
ax3.plot(np.linspace(-256/2,256/2-1,256)*125/256,spectrum1[:256].astype(float),'b-')
ax3.set(xlabel='freq (MHz)',ylabel='power',title='Ch1')
ax3.set_xlim(0,50)
plt.show()
