Hi Colm, We discussed this and it appears that only two of the ADC's and DAC's will be routed to connectors, hence the 2x2. Dan has already asked Xilinx whether there is any scope to bring additional channels out to headers or other low cost connectors. We await an answer.
Regards, Francois On Tue, 16 Feb 2021 at 13:45, Colm Bracken <[email protected]> wrote: > Hi Dan, > > Thanks for the info. > Do you happen to know what the '2x2' signifies in the name RF SoC 2x2? > I was thinking 2 DACs and 2 ADCs, but you mentioned that it will have the > XCZU28DR chip which hosts 8 ADCS and 8 DACs. > Looking forward to learning more about this board! > > Thanks, > Colm > > On Wed, 10 Feb 2021 at 19:01, Dan Werthimer <[email protected]> wrote: > >> >> >> dear casper community, >> >> please see email below from xilinx's patrick lysaght, >> about their new low cost RFSOC board for academia, >> and the february 28 tutorial about this board. >> >> best wishes, >> >> dan >> >> ---------- Forwarded message --------- >> Date: Wed, Feb 10, 2021 at 10:00 AM >> Subject: Emailing: isfpga_rfsoc_2x2_tutorial.jpg >> >> >> Dear Friends >> >> I hope you are all doing well in 2021. I have some good news that I >> would like to share with you. At the end of Feb, we will launch a new >> RFSoC platform for academia. It features a new board, the RFSoC 2x2, >> supported with open source designs and teaching material. We will be >> hosting a tutorial on Sunday 28th Feb from 8 - 10 AM PST as part of the >> ISFPGA 2021 conference (https://isfpga.org/) to announce and introduce >> the new RFSoC 2x2 platform. Everyone is welcome to attend the tutorial and >> registration is free for students. >> >> Would you kindly share this invitation with the CASPER community? For >> those who would like to attend, links to the tutorial site and the >> registration pages are provided below. I have also attached a graphic >> summarizing the tutorial. >> >> Best .. Patrick >> >> More details ... >> A Low-Cost Teaching and Research Platform Based on Xilinx RFSoC >> Technology and the PYNQ Framework >> Time: February 28, 8:00 AM - 10:00 AM PST >> Organizer: Patrick Lysaght (Xilinx), Robert W. Stewart (Strathclyde) >> >> The Xilinx Zynq(r) UltraScale+(tm) RFSoC architecture integrates ZU+ >> MPSoCs with state-of-the-art, analog-to-digital (ADC) and digital-to-analog >> (DAC) data converters. The combination of banks of high-precision data >> converters, capable of processing multi giga samples of data per second, >> along with FPGA fabric and ARM processors creates a uniquely powerful >> family architecture. RFSoC technology re-defines what is possible in >> applications such as software defined radio (SDR) and advanced >> instrumentation. >> This tutorial introduces a new low-cost teaching and research platform >> for RFSoC, designed especially for academia. The platform exploits the PYNQ >> open-source framework to provide a highly intuitive user system interface >> incorporating Linux, Python and Jupyter notebooks. It also comes with a >> suite of open-source teaching resources including videos, notebooks and >> design examples. >> We will demonstrate the benefits of integrating direct RF sampling data >> converters by introducing a novel, open-source spectrum analyzer built >> using the new board. This RFSoC design exploits advanced signal processing >> techniques, including higher-order Nyquist zones, to demonstrate >> performance that has only previously been achieved on very high-end >> instrumentation. Using the spectrum analyzer example, we will also >> demonstrate new approaches to the rapid prototyping of graphical user >> interfaces for research demonstrators. >> >> Links ... >> ISFPGA tutorial page: http://bit.ly/ISFPGA_rfsoc2x2 >> Register for ISFPGA & tutorial here: http://bit.ly/ISFPGA_rfsoc2x2 >> #Xilinx #RFSoC >> >> >> >> >> This email and any attachments are intended for the sole use of the named >> recipient(s) and contain(s) confidential information that may be >> proprietary, privileged or copyrighted under applicable law. If you are not >> the intended recipient, do not read, copy, or forward this email message or >> any attachments. Delete this email message and any attachments immediately. >> >> -- >> You received this message because you are subscribed to the Google Groups >> "[email protected]" group. >> To unsubscribe from this group and stop receiving emails from it, send an >> email to [email protected]. >> To view this discussion on the web visit >> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAGHS_vHaL9wJFZjVWYoXPTZfwm%2BE%2BNJPd8QVifZ6-MqhgNX6BQ%40mail.gmail.com >> <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAGHS_vHaL9wJFZjVWYoXPTZfwm%2BE%2BNJPd8QVifZ6-MqhgNX6BQ%40mail.gmail.com?utm_medium=email&utm_source=footer> >> . >> > > > -- > > *Dr Colm Bracken* > Lecturer > Maynooth University Experimental Physics > > > Maynooth University, Maynooth, Co. Kildare, Ireland. > > T: +353 1 708 3641 > E: [email protected] W: www.maynoothuniversity.ie > > Follow my work on https://nuim.academia.edu/ColmBracken > > > > And > > > Research Associate > > Astronomy & Astrophysics Section > School of Cosmic Physics > Dublin Institute for Advanced Studies > 31 Fitzwilliam Place > Dublin 2, D02 XF86 > > > > T: +353 1 440 6656 ext 352 > E: [email protected] W: www.dias.ie/2017/06/22/dr-colm-bracken > > Follow my work on https://nuim.academia.edu/ColmBracken > > -- > You received this message because you are subscribed to the Google Groups " > [email protected]" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > To view this discussion on the web visit > https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAEx9wh-fKiwL4k619r7CSkG9aij%2B5pgTQ6Gkr7ntmR7SZQmHig%40mail.gmail.com > <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAEx9wh-fKiwL4k619r7CSkG9aij%2B5pgTQ6Gkr7ntmR7SZQmHig%40mail.gmail.com?utm_medium=email&utm_source=footer> > . > -- You received this message because you are subscribed to the Google Groups "[email protected]" group. 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