perhaps there's an easier way casperite's could get about 10Gbit/sec
ethernet from the RFSOC2x2:

the RFSOC2x2 has a pair of USB3.0 connectors.
in theory, each USB3.0 connector can run up to 4.8 Gbit/sec.
these USB ports can be converted to high speed ethernet using adapter boxes
like these:

https://www.trendnet.com/products/usb-c-5g-ethernet-adapter/usb-c-3-1-to-5gbase-t-ethernet-adapter-TUC-ET5G
https://www.trendnet.com/products/usb/USB-C-3.1-to-2.5GBASE-T-Ethernet-Adapter-TUC-ET2G


best wishes,

dan

On Tue, Mar 9, 2021 at 2:13 PM Dan Werthimer <[email protected]> wrote:

>
>
> it's not easy to get high bandwidth ethernet data off this RFSOC2x2 board:
> there's a standard parallel zysygy data connector  on the board (13 LVDS
> pairs or 26 single ended),
> and there are small commercial $300 fpga boards that have several
> zysygy connectors
> including high speed serdes zysygy connectors, and there are $50 SFP+
> zysygy mezzanine boards...
>
> best wishes,
>
> dan
> .
>
>
>
> Dan Werthimer
> Marilyn and Watson Alberts Chair
> Astronomy Dept and Space Sciences Lab
> University of California, Berkeley
>
>
> On Tue, Mar 9, 2021 at 1:59 PM 'Timothy Bateman' via
> [email protected] <[email protected]> wrote:
>
>> The Ethernet interface is only 1GbE ? An SFP+ would make it a lot more
>> useful ....
>> ------------------------------
>> *From:* Forbes, David C - (dforbes) <[email protected]>
>> *Sent:* Wednesday, 10 March 2021 2:33 AM
>> *To:* [email protected] <[email protected]>
>> *Subject:* RE: [EXT]Re: [casper] low cost academic xilinx RFSOC board -
>> feb 28 tutorial 8am pacific
>>
>> Kaj,
>>
>> A quick Google search reveals all...
>>
>>
>> https://protect-au.mimecast.com/s/FqVDCp81lrtnNJzv7hPwTs9?domain=xilinx.com
>>
>>
>> -----Original Message-----
>> From: Kaj Wiik <[email protected]>
>> Sent: Tuesday, March 9, 2021 7:21 AM
>> To: [email protected]
>> Subject: [EXT]Re: [casper] low cost academic xilinx RFSOC board - feb 28
>> tutorial 8am pacific
>>
>> External Email
>>
>> Hi!
>>
>> Did the tutorial reveal any further info (spec sheet, availability) of
>> this board?
>>
>> Thanks,
>> Kaj
>>
>>
>> On 16/02/2021 16:36, Francois Kapp wrote:
>> > Hi Colm,
>> >
>> > We discussed this and it appears that only two of the ADC's and DAC's
>> > will be routed to connectors, hence the 2x2.  Dan has already asked
>> > Xilinx whether there is any scope to bring additional channels out to
>> > headers or other low cost connectors.  We await an answer.
>> >
>> > Regards,
>> > Francois
>> >
>> > On Tue, 16 Feb 2021 at 13:45, Colm Bracken <[email protected]
>> > <mailto:[email protected] <[email protected]>>> wrote:
>> >
>> >     Hi Dan,
>> >
>> >     Thanks for the info.
>> >     Do you happen to know what the '2x2' signifies in the name RF SoC
>> 2x2?
>> >     I was thinking 2 DACs and 2 ADCs, but you mentioned that it will
>> have the
>> >     XCZU28DR chip which hosts 8 ADCS and 8 DACs.
>> >     Looking forward to learning more about this board!
>> >
>> >     Thanks,
>> >     Colm
>> >
>> >     On Wed, 10 Feb 2021 at 19:01, Dan Werthimer <[email protected]
>> >     <mailto:[email protected] <[email protected]>>> wrote:
>> >
>> >
>> >
>> >         dear casper community,
>> >
>> >         please see email below from xilinx's patrick lysaght,
>> >         about their new low cost RFSOC board for academia,
>> >         and the february 28 tutorial about this board.
>> >
>> >         best wishes,
>> >
>> >         dan
>> >
>> >         ---------- Forwarded message ---------
>> >         Date: Wed, Feb 10, 2021 at 10:00 AM
>> >         Subject: Emailing: isfpga_rfsoc_2x2_tutorial.jpg
>> >
>> >
>> >           Dear Friends
>> >
>> >         I hope you are all doing well in 2021.  I have some good news
>> that I
>> >         would like to share with you.  At the end of Feb, we will
>> launch a new
>> >         RFSoC platform for academia.  It features a new board, the
>> RFSoC 2x2,
>> >         supported with open source designs and teaching material.  We
>> will be
>> >         hosting a tutorial on Sunday 28th Feb from 8 - 10 AM PST as
>> part of the
>> >         ISFPGA 2021 conference (
>> https://protect-au.mimecast.com/s/otPXCq71mwf8PxOzVtXa1pM?domain=isfpga.org
>> <
>> https://protect-au.mimecast.com/s/otPXCq71mwf8PxOzVtXa1pM?domain=isfpga.org/>)
>> to
>> >         announce and introduce the new RFSoC 2x2 platform.  Everyone is
>> welcome
>> >         to attend the tutorial and registration is free for students.
>> >
>> >         Would you kindly share this invitation with the CASPER
>> community?  For
>> >         those who would like to attend, links to the tutorial site and
>> the
>> >         registration pages are provided below.  I have also attached a
>> graphic
>> >         summarizing the tutorial.
>> >
>> >         Best .. Patrick
>> >
>> >         More details ...
>> >         A Low-Cost Teaching and Research Platform Based on Xilinx RFSoC
>> >         Technology and the PYNQ Framework
>> >         Time: February 28, 8:00 AM - 10:00 AM PST
>> >         Organizer: Patrick Lysaght (Xilinx), Robert W. Stewart
>> > (Strathclyde)
>> >
>> >         The Xilinx Zynq(r) UltraScale+(tm) RFSoC architecture
>> integrates ZU+
>> >         MPSoCs with state-of-the-art, analog-to-digital (ADC) and
>> >         digital-to-analog (DAC) data converters. The combination of
>> banks of
>> >         high-precision data converters, capable of processing multi
>> giga samples
>> >         of data per second, along with FPGA fabric and ARM processors
>> creates a
>> >         uniquely powerful family architecture.  RFSoC technology
>> re-defines what
>> >         is possible in applications such as software defined radio
>> (SDR) and
>> >         advanced instrumentation.
>> >         This tutorial introduces a new low-cost teaching and research
>> platform
>> >         for RFSoC, designed especially for academia. The platform
>> exploits the
>> >         PYNQ open-source framework to provide a highly intuitive user
>> system
>> >         interface incorporating Linux, Python and Jupyter notebooks. It
>> also
>> >         comes with a suite of open-source teaching resources including
>> videos,
>> >         notebooks and design examples.
>> >         We will demonstrate the benefits of integrating direct RF
>> sampling data
>> >         converters by introducing  a novel, open-source spectrum
>> analyzer built
>> >         using the new board. This RFSoC design exploits advanced signal
>> >         processing techniques, including higher-order Nyquist zones, to
>> >         demonstrate performance that has only previously been achieved
>> on very
>> >         high-end instrumentation. Using the spectrum analyzer example,
>> we will
>> >         also demonstrate new approaches to the rapid prototyping of
>> graphical
>> >         user interfaces for research demonstrators.
>> >
>> >         Links ...
>> >         ISFPGA tutorial page:
>> https://protect-au.mimecast.com/s/Kk1lCr81nyt80zA1Wt4Ec6N?domain=bit.ly
>> >         <
>> https://protect-au.mimecast.com/s/Kk1lCr81nyt80zA1Wt4Ec6N?domain=bit.ly>
>> >         Register for ISFPGA & tutorial here:
>> https://protect-au.mimecast.com/s/Kk1lCr81nyt80zA1Wt4Ec6N?domain=bit.ly
>> >         <
>> https://protect-au.mimecast.com/s/Kk1lCr81nyt80zA1Wt4Ec6N?domain=bit.ly>
>> #Xilinx #RFSoC
>> >
>> >
>> >
>> >
>> >         This email and any attachments are intended for the sole use of
>> the
>> >         named recipient(s) and contain(s) confidential information that
>> may be
>> >         proprietary, privileged or copyrighted under applicable law. If
>> you are
>> >         not the intended recipient, do not read, copy, or forward this
>> email
>> >         message or any attachments. Delete this email message and any
>> >         attachments immediately.
>> >
>> >         --
>> >         You received this message because you are subscribed to the
>> Google
>> >         Groups "[email protected] <
>> mailto:[email protected] <[email protected]>>" group.
>> >         To unsubscribe from this group and stop receiving emails from
>> it, send
>> >         an email to [email protected]
>> >         <mailto:[email protected]
>> <[email protected]>>.
>> >         To view this discussion on the web visit
>> >
>> https://protect-au.mimecast.com/s/SzKaCvl1rKi7jPW2RcASrjK?domain=groups.google.com
>> >         <
>> https://protect-au.mimecast.com/s/4rHcCwV1vMfGz4LA2u1EC_y?domain=groups.google.com
>> >.
>> >
>> >
>> >
>> >     --
>> >
>> >     *Dr Colm Bracken*
>> >     Lecturer
>> >     Maynooth University Experimental Physics
>> >
>> >
>> >     Maynooth University, Maynooth, Co. Kildare, Ireland.
>> >
>> >     T: +353 1 708 3641
>> >     E: [email protected] <mailto:[email protected]
>> <[email protected]>> W:
>> >     www.maynoothuniversity.ie <
>> https://protect-au.mimecast.com/s/Ujc3CxngwOf14gJ9zTWHEyb?domain=maynoothuniversity.ie
>> >
>> >
>> >     Follow my work on
>> https://protect-au.mimecast.com/s/17jCCyojxQTrzQN0piPQjZB?domain=nuim.academia.edu
>> >     <
>> https://protect-au.mimecast.com/s/17jCCyojxQTrzQN0piPQjZB?domain=nuim.academia.edu
>> >
>> >
>> >     And
>> >
>> >
>> >     Research Associate
>> >
>> >     Astronomy & Astrophysics Section
>> >     School of Cosmic Physics
>> >     Dublin Institute for Advanced Studies
>> >     31 Fitzwilliam Place
>> >     Dublin 2, D02 XF86
>> >
>> >
>> >
>> >     T: +353 1 440 6656 ext 352
>> >     E: [email protected] <mailto:[email protected]
>> <[email protected]>> W:
>> >     www.dias.ie/2017/06/22/dr-colm-bracken
>> >     <
>> https://protect-au.mimecast.com/s/BtIxCzvkyVCMpyRx7IMJghl?domain=dias.ie>
>> >
>> >     Follow my work on
>> https://protect-au.mimecast.com/s/17jCCyojxQTrzQN0piPQjZB?domain=nuim.academia.edu
>> >     <
>> https://protect-au.mimecast.com/s/17jCCyojxQTrzQN0piPQjZB?domain=nuim.academia.edu
>> >
>> >
>> >     --
>> >     You received this message because you are subscribed to the Google
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>> https://protect-au.mimecast.com/s/jpTqCANpgjCN3P9n8cBfV8e?domain=groups.google.com
>> >     <
>> https://protect-au.mimecast.com/s/d0zLCBNqjlC79kVMycQUNDv?domain=groups.google.com
>> >.
>> >
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>> https://protect-au.mimecast.com/s/zjqWCE8wmrt3JzWgYIkCRGn?domain=groups.google.com
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