Hello Amit,
Is there any good document available for changing the
configurations for the new projects to be created and also new containers. I am
trying to run different examples from codezero-toolkit-0.5.0 on Pandaboard
other than Hello_World.
Following is the output for thread_demo:
-------------------
U-Boot 1.1.4-g0a8bcfef-dirty (Jul 17 2011 - 13:16:57)
Load address: 0x80e80000
DRAM: 512 MB
Flash: 0 kB
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: KS8851SNL
Hit any key to stop autoboot: 0
mmc read: Invalid size
384046 bytes read
S# Starting application at 0xBC500000 ...
ELF Loader: Loader image size: 296KB, placed at physical 0xbc500000 - 0xbc54a1e4
Loading the kernel...
Entry point: 0x80008000
Copying to range from 0x80008000 to 0x80025018 of size: 0x1d018
Clearing memory... starting from 80025018, size: 6ff8
Copying to range from 0x80030000 to 0x8003c1b8 of size: 0xc1b8
Clearing memory... starting from 8003c1b8, size: 0
Loading containers...
Loading section .cont.0 from top-level elf file.
Loading .img.0 section image...
Entry point: 0xc0000000
Copying to range from 0x84003b24 to 0x84003b2c of size: 0x8
Clearing memory... starting from 84003b2c, size: 0
Copying to range from 0x84000000 to 0x84003b2c of size: 0x3b2c
Clearing memory... starting from 84003b2c, size: 0
Copying to range from 0x84004000 to 0x840040b4 of size: 0xb4
Clearing memory... starting from 840040b4, size: 115f78
Total of 1 images in this container.
Total of 1 container images.
elf-loader: kernel entry point is 0x80008000
elf-loader: Starting kernel
code0: start kernel...
code0: Init kernel mappings...
code0: Virtual memory enabled.
code0: CPU: Cortex-A9, r2p10
code0: CPU supports: ThumbEE/Thumb2/Jazelle/TrustZone
code0: D-cache: PIPT, I-cache: VIPT
code0: Cache Write-back granule: 32 bytes
code0: Exclusive reservation granule: 32 bytes
code0: D-cache minimum line: 32 bytes
code0: I-cache minimum line: 32 bytes
code0: 1 Levels of caches.
code0: Required LoUUP/LoC/LoUIS levels: 1, 1, 1
code0: L1 cache(s): 32Kb, 4-way, 256 sets, 32-byte lines.
code0: Separate I+D caches with WriteAlloc/ReadAlloc/WriteBack/ support.
code0: Bringing up CPU1
code0: CPU1: Virtual memory enabled.
code0: CPU1: Initialized.
code0: SMP: 2 CPU cluster, CPU0/1/ are participating in SMP
code0: Kernel area 0xf0008000 - 0xf003d000 remapped as 53 pages
code0: Kernel built on Aug 19 2011, 14:01:38
code0: Mapping 0x3000 bytes as RX from 0x84000000 physical to 0xc0000000
virtual for project0
code0: Mapping 0x2000 bytes as RW from 0x84003000 physical to 0xc0003000
virtual for project0
fault_ipc_to_pager: Sending ipc from 1 to 1, faulty_address=0xc011a028, faulty
pc=0xc00024f4
tid=0x00000001
Unhandled kernel data abort at address 0x00000008
FAR:0x00000008
PC:0xf000e380
Unhandled kernel abort.
Kernel panic.
Halting system...
-------------------
Reading/Analysing more about it to understand if i missed something. Please let
me know your inputs.
Thanks in Advance.
Regards,
Kk
________________________________
From: Kaushik karandikar <kaushikkarandi...@yahoo.com>
To: "amit.maha...@b-labs.com" <amit.maha...@b-labs.com>
Cc: "codezero-devel@lists.l4dev.org" <codezero-devel@lists.l4dev.org>
Sent: Tuesday, 29 May 2012 11:50 AM
Subject: Re: [codezero-devel] CodeZero on PandaBoard ES
Hello Amit,
Thanks for the quick response and resolution of the
query in short time. I could run the Hello World example. Will also explore
the other examples and final aim is to run ubuntu kernel on codezero
microkernel.
Thanks again for the quick help.
Regards,
Kk
From: Amit Mahajan <amit.maha...@b-labs.com>
To: Kaushik karandikar <kaushikkarandi...@yahoo.com>
Sent: Tuesday, 29 May 2012 11:16 AM
Subject: Re: [codezero-devel] CodeZero on PandaBoard ES
On Mon, 2012-05-28 at 22:38 -0700, Kaushik karandikar wrote:
> Hi Amit,
> Yes its the same binary from prebuilt/u-boot.bin from
> codezero-toolkit.
>
> Regards,
> Kaushik
>
http://lists.l4dev.org/pipermail/codezero-devel_lists.l4dev.org/2012-May/000286.html
Check the above thread. Fabio was able to run the toolkit release on ES.
>
>
>
>
--
Thanks,
Amit Mahajan
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