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commit 84089dacfdc076a8ca86db7901f57e92181cc231 Author: raiden00pl <[email protected]> AuthorDate: Sat Oct 10 18:01:43 2026 +0200 boards/arm/stm32f2/nucleo-f207zg: fix APB2 clock PPRE2 was programmed as HCLK / 1 while PCLK2 was defined as HCLK / 2, so APB2 ran at twice the defined frequency and the APB2 timers ran twice as fast as configured. Program HCLK / 2 as defined and clock the APB2 timers at 2 x PCLK2. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- boards/arm/stm32f2/nucleo-f207zg/include/board.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/boards/arm/stm32f2/nucleo-f207zg/include/board.h b/boards/arm/stm32f2/nucleo-f207zg/include/board.h index 6cf3637806b..1043a2d7bfc 100644 --- a/boards/arm/stm32f2/nucleo-f207zg/include/board.h +++ b/boards/arm/stm32f2/nucleo-f207zg/include/board.h @@ -99,16 +99,16 @@ /* APB2 clock (PCLK2) is HCLK/2 (50MHz) */ -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 2 */ +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) /* Timers driven from APB2 will be twice PCLK2 (100Mhz) */ -#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timers driven from APB1 will be twice PCLK1 (50MHz) */
