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commit 550f94b580ba7b08751f7dea480fafc1bd1800b4 Author: raiden00pl <[email protected]> AuthorDate: Fri Jun 5 18:58:42 2026 +0200 arch/arm/src/stm32: unify TIM1/TIM8 interrupt vector names across families The TIM1 and TIM8 interrupt vectors are the same interrupts on every family, but were named inconsistently: - F1/F2/F3/F4/F7/G4/H7/L4/WB/WL5: STM32_IRQ_TIM1UP / TIM1BRK / TIM1TRGCOM / TIM1CC - H5/L5/U5/N6/U3/C5: STM32_IRQ_TIM1_UP / _BRK / _TRG_COM / _CC - Cortex-M0 (C0/F0/G0/U0): combined STM32_IRQ_TIM1_BRK (BRK_UP_TRG_COM) Standardize on the majority no-underscore form so a driver can refer to e.g. STM32_IRQ_TIM1UP on any family. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- arch/arm/include/stm32c0/irq.h | 4 ++-- arch/arm/include/stm32c5/stm32_irq.h | 16 +++++++-------- arch/arm/include/stm32f0/irq.h | 4 ++-- arch/arm/include/stm32g0/irq.h | 4 ++-- arch/arm/include/stm32h5/stm32h5xx_irq.h | 16 +++++++-------- arch/arm/include/stm32l5/stm32l562xx_irq.h | 16 +++++++-------- arch/arm/include/stm32n6/stm32n6xx_irq.h | 16 +++++++-------- arch/arm/include/stm32u0/irq.h | 4 ++-- arch/arm/include/stm32u3/stm32u3c5xx_irq.h | 16 +++++++-------- arch/arm/include/stm32u5/stm32u5xx_irq.h | 16 +++++++-------- arch/arm/src/common/stm32/stm32_pulsecount.c | 25 +++++------------------- arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c | 2 +- arch/arm/src/common/stm32/stm32_tim_m0_v1.c | 2 +- arch/arm/src/stm32h5/stm32_tim.c | 4 ++-- 14 files changed, 65 insertions(+), 80 deletions(-) diff --git a/arch/arm/include/stm32c0/irq.h b/arch/arm/include/stm32c0/irq.h index aba16028025..6088325be6d 100644 --- a/arch/arm/include/stm32c0/irq.h +++ b/arch/arm/include/stm32c0/irq.h @@ -86,8 +86,8 @@ #define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */ #define STM32_IRQ_DMAMUX (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX */ #define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ #define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */ #define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */ #define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */ diff --git a/arch/arm/include/stm32c5/stm32_irq.h b/arch/arm/include/stm32c5/stm32_irq.h index 4e28aca6b69..65f235e489b 100644 --- a/arch/arm/include/stm32c5/stm32_irq.h +++ b/arch/arm/include/stm32c5/stm32_irq.h @@ -97,14 +97,14 @@ #define STM32_IRQ_ADC2 (STM32_IRQ_FIRST + 33) #define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 34) #define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 35) -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 36) +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 36) #define STM32_IRQ_TIM1_TERR (STM32_IRQ_FIRST + 36) #define STM32_IRQ_TIM1_IERR (STM32_IRQ_FIRST + 36) -#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 37) -#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 38) +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 37) +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 38) #define STM32_IRQ_TIM1_DIR (STM32_IRQ_FIRST + 38) #define STM32_IRQ_TIM1_IDX (STM32_IRQ_FIRST + 38) -#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 39) +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 39) #define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 40) #define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 41) #define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 42) @@ -137,14 +137,14 @@ #define STM32_IRQ_HASH (STM32_IRQ_FIRST + 69) #define STM32_IRQ_I2C2_EV (STM32_IRQ_FIRST + 70) #define STM32_IRQ_I2C2_ER (STM32_IRQ_FIRST + 71) -#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 72) +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 72) #define STM32_IRQ_TIM8_TERR (STM32_IRQ_FIRST + 72) #define STM32_IRQ_TIM8_IERR (STM32_IRQ_FIRST + 72) -#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 73) -#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 74) +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 73) +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 74) #define STM32_IRQ_TIM8_DIR (STM32_IRQ_FIRST + 74) #define STM32_IRQ_TIM8_IDX (STM32_IRQ_FIRST + 74) -#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 75) +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 75) #define STM32_IRQ_COMP1 (STM32_IRQ_FIRST + 76) #define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 77) #define STM32_IRQ_LPDMA2_CH0 (STM32_IRQ_FIRST + 78) diff --git a/arch/arm/include/stm32f0/irq.h b/arch/arm/include/stm32f0/irq.h index c142f9068be..02cb919f01d 100644 --- a/arch/arm/include/stm32f0/irq.h +++ b/arch/arm/include/stm32f0/irq.h @@ -91,8 +91,8 @@ #define STM32_IRQ_DMA2CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH5 */ #define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */ #define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ #define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */ #define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */ #define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */ diff --git a/arch/arm/include/stm32g0/irq.h b/arch/arm/include/stm32g0/irq.h index 4d4b3c98ff4..184204511f9 100644 --- a/arch/arm/include/stm32g0/irq.h +++ b/arch/arm/include/stm32g0/irq.h @@ -120,8 +120,8 @@ # define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */ #endif -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ #if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ defined(CONFIG_ARCH_CHIP_STM32G070RB) diff --git a/arch/arm/include/stm32h5/stm32h5xx_irq.h b/arch/arm/include/stm32h5/stm32h5xx_irq.h index b1fc1a6c13c..7ba0c55018c 100644 --- a/arch/arm/include/stm32h5/stm32h5xx_irq.h +++ b/arch/arm/include/stm32h5/stm32h5xx_irq.h @@ -88,10 +88,10 @@ # define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 38) /* 38: DAC global interrupt */ # define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */ # define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */ -# define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ -# define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ -# define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ -# define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ +# define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ +# define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ +# define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ +# define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ # define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ # define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ # define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ @@ -112,10 +112,10 @@ # define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 62) /* 62: UART5 global interrupt */ # define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 63) /* 63: LPUART1 global interrupt */ # define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 64) /* 64: LPTIM1 global interrupt */ -# define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 65) /* 65: TIM8_BRK global interrupt */ -# define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 66) /* 66: TIM8_UP global interrupt */ -# define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 67) /* 67: TIM8_TRG_COM global interrupt */ -# define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 68) /* 68: TIM8_CC global interrupt */ +# define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 65) /* 65: TIM8_BRK global interrupt */ +# define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 66) /* 66: TIM8_UP global interrupt */ +# define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 67) /* 67: TIM8_TRG_COM global interrupt */ +# define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 68) /* 68: TIM8_CC global interrupt */ # define STM32_IRQ_ADC2 (STM32_IRQ_FIRST + 69) /* 69: ADC2 global interrupt */ # define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 70) /* 70: LPTIM2 global interrupt */ # define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 71) /* 71: TIM15 global interrupt */ diff --git a/arch/arm/include/stm32l5/stm32l562xx_irq.h b/arch/arm/include/stm32l5/stm32l562xx_irq.h index 35e326d15b0..b60e9e85244 100644 --- a/arch/arm/include/stm32l5/stm32l562xx_irq.h +++ b/arch/arm/include/stm32l5/stm32l562xx_irq.h @@ -91,20 +91,20 @@ #define STM32_IRQ_DAC (STM32_IRQ_FIRST + 38) /* 38: DAC global interrupt */ #define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */ #define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ -#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ -#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ #define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ #define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ #define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ #define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */ #define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */ #define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */ -#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */ -#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */ -#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ -#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ #define STM32_IRQ_I2C1_EV (STM32_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */ #define STM32_IRQ_I2C1_ER (STM32_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */ #define STM32_IRQ_I2C2_EV (STM32_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */ diff --git a/arch/arm/include/stm32n6/stm32n6xx_irq.h b/arch/arm/include/stm32n6/stm32n6xx_irq.h index ef186921d27..71af964ef67 100644 --- a/arch/arm/include/stm32n6/stm32n6xx_irq.h +++ b/arch/arm/include/stm32n6/stm32n6xx_irq.h @@ -145,20 +145,20 @@ #define STM32_IRQ_I3C1_ER (STM32_IRQ_FIRST + 109) /* 109: I3C1 error interrupt */ #define STM32_IRQ_I3C2_EV (STM32_IRQ_FIRST + 110) /* 110: I3C2 event interrupt */ #define STM32_IRQ_I3C2_ER (STM32_IRQ_FIRST + 111) /* 111: I3C2 error interrupt */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 112) /* 112: TIM1 Break interrupt */ -#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 113) /* 113: TIM1 Update interrupt */ -#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 114) /* 114: TIM1 Trigger and Commutation interrupt */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 115) /* 115: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 112) /* 112: TIM1 Break interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 113) /* 113: TIM1 Update interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 114) /* 114: TIM1 Trigger and Commutation interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 115) /* 115: TIM1 Capture Compare interrupt */ #define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 116) /* 116: TIM2 global interrupt */ #define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 117) /* 117: TIM3 global interrupt */ #define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 118) /* 118: TIM4 global interrupt */ #define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 119) /* 119: TIM5 global interrupt */ #define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 120) /* 120: TIM6 global interrupt */ #define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 121) /* 121: TIM7 global interrupt */ -#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 122) /* 122: TIM8 Break interrupt */ -#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 123) /* 123: TIM8 Update interrupt */ -#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 124) /* 124: TIM8 Trigger and Commutation interrupt */ -#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 125) /* 125: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 122) /* 122: TIM8 Break interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 123) /* 123: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 124) /* 124: TIM8 Trigger and Commutation interrupt */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 125) /* 125: TIM8 Capture Compare interrupt */ #define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 126) /* 126: TIM9 global interrupt */ #define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 127) /* 127: TIM10 global interrupt */ #define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 128) /* 128: TIM11 global interrupt */ diff --git a/arch/arm/include/stm32u0/irq.h b/arch/arm/include/stm32u0/irq.h index e13dcdf4fea..6696c6775b9 100644 --- a/arch/arm/include/stm32u0/irq.h +++ b/arch/arm/include/stm32u0/irq.h @@ -94,8 +94,8 @@ #define STM32_IRQ_DMAMUX (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX overrun */ #define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */ #define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP1, COMP2 */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ #define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */ #define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */ #define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */ diff --git a/arch/arm/include/stm32u3/stm32u3c5xx_irq.h b/arch/arm/include/stm32u3/stm32u3c5xx_irq.h index c617bc43f08..2a61feaa421 100644 --- a/arch/arm/include/stm32u3/stm32u3c5xx_irq.h +++ b/arch/arm/include/stm32u3/stm32u3c5xx_irq.h @@ -89,14 +89,14 @@ #define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 38) /* 38: DAC1 global interrupt */ #define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1 Interrupt 0 */ #define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1 Interrupt 1 */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ #define STM32_IRQ_TIM1_TERR (STM32_IRQ_FIRST + 41) /* 41: TIM1 transition error */ #define STM32_IRQ_TIM1_IERR (STM32_IRQ_FIRST + 41) /* 41: TIM1 index error */ -#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ -#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ #define STM32_IRQ_TIM1_DIR (STM32_IRQ_FIRST + 43) /* 43: TIM1 direction change interrupt */ #define STM32_IRQ_TIM1_IDX (STM32_IRQ_FIRST + 43) /* 43: TIM1 index */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ #define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ #define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ #define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ @@ -145,14 +145,14 @@ #define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 99) /* 99: SPI3 global interrupt */ #define STM32_IRQ_I3C2_EV (STM32_IRQ_FIRST + 100) /* 100: I3C2 event interrupt */ #define STM32_IRQ_I3C2_ER (STM32_IRQ_FIRST + 101) /* 101: I3C2 error interrupt */ -#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 102) /* 102: TIM8 break */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 102) /* 102: TIM8 break */ #define STM32_IRQ_TIM8_TERR (STM32_IRQ_FIRST + 102) /* 102: TIM8 transition error */ #define STM32_IRQ_TIM8_IERR (STM32_IRQ_FIRST + 102) /* 102: TIM8 index error */ -#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 103) /* 103: TIM8 update */ -#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 104) /* 104: TIM8 trigger and communication */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 103) /* 103: TIM8 update */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 104) /* 104: TIM8 trigger and communication */ #define STM32_IRQ_TIM8_DIR (STM32_IRQ_FIRST + 104) /* 104: TIM8 direction change interrupt */ #define STM32_IRQ_TIM8_IDX (STM32_IRQ_FIRST + 104) /* 104: TIM8 index */ -#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 105) /* 105: TIM8 capture compare interrupt */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 105) /* 105: TIM8 capture compare interrupt */ #define STM32_IRQ_ICACHE (STM32_IRQ_FIRST + 107) /* 107: Instruction cache global interrupt */ #define STM32_IRQ_LPTIM4 (STM32_IRQ_FIRST + 110) /* 110: LPTIM4 global interrupt */ #define STM32_IRQ_ADF1 (STM32_IRQ_FIRST + 112) /* 112: ADF1 global interrupt */ diff --git a/arch/arm/include/stm32u5/stm32u5xx_irq.h b/arch/arm/include/stm32u5/stm32u5xx_irq.h index bb629ca1eeb..57a3fe56b36 100644 --- a/arch/arm/include/stm32u5/stm32u5xx_irq.h +++ b/arch/arm/include/stm32u5/stm32u5xx_irq.h @@ -90,28 +90,28 @@ #define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 38) /* 38: DAC1 global interrupt */ #define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1 Interrupt 0 */ #define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1 Interrupt 1 */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ #define STM32_IRQ_TIM1_TERR (STM32_IRQ_FIRST + 41) /* 41: TIM1 transition error */ #define STM32_IRQ_TIM1_IERR (STM32_IRQ_FIRST + 41) /* 41: TIM1 index error */ -#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ -#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ #define STM32_IRQ_TIM1_DIR (STM32_IRQ_FIRST + 43) /* 43: TIM1 direction change interrupt */ #define STM32_IRQ_TIM1_IDX (STM32_IRQ_FIRST + 43) /* 43: TIM1 index */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ #define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ #define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ #define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ #define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */ #define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */ #define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */ -#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */ #define STM32_IRQ_TIM8_TERR (STM32_IRQ_FIRST + 51) /* 51: TIM8 transition error */ #define STM32_IRQ_TIM8_IERR (STM32_IRQ_FIRST + 51) /* 51: TIM8 index error */ -#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */ -#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ #define STM32_IRQ_TIM8_DIR (STM32_IRQ_FIRST + 53) /* 53: TIM8 direction change interrupt */ #define STM32_IRQ_TIM8_IDX (STM32_IRQ_FIRST + 53) /* 53: TIM8 index */ -#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ #define STM32_IRQ_I2C1_EV (STM32_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */ #define STM32_IRQ_I2C1_ER (STM32_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */ #define STM32_IRQ_I2C2_EV (STM32_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */ diff --git a/arch/arm/src/common/stm32/stm32_pulsecount.c b/arch/arm/src/common/stm32/stm32_pulsecount.c index 0927f3c4ee7..e5e746a13eb 100644 --- a/arch/arm/src/common/stm32/stm32_pulsecount.c +++ b/arch/arm/src/common/stm32/stm32_pulsecount.c @@ -70,24 +70,6 @@ #define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR #define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST -/* The TIM1/TIM8 update-event interrupt vector is named differently across - * families. This will be unified later. - */ - -#if defined(STM32_IRQ_TIM1UP) -# define PULSECOUNT_TIM1_IRQ STM32_IRQ_TIM1UP -#elif defined(STM32_IRQ_TIM1_UP) -# define PULSECOUNT_TIM1_IRQ STM32_IRQ_TIM1_UP -#elif defined(STM32_IRQ_TIM1_BRK) -# define PULSECOUNT_TIM1_IRQ STM32_IRQ_TIM1_BRK -#endif - -#if defined(STM32_IRQ_TIM8UP) -# define PULSECOUNT_TIM8_IRQ STM32_IRQ_TIM8UP -#elif defined(STM32_IRQ_TIM8_UP) -# define PULSECOUNT_TIM8_IRQ STM32_IRQ_TIM8_UP -#endif - /* Default GPIO pins state */ #if defined(CONFIG_STM32_STM32F10XX) @@ -269,7 +251,7 @@ static struct stm32_tim_s g_pulsecount1dev = .timid = 1, .timtype = TIMTYPE_TIM1, .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, - .irq = PULSECOUNT_TIM1_IRQ, + .irq = STM32_IRQ_TIM1UP, .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; @@ -320,7 +302,7 @@ static struct stm32_tim_s g_pulsecount8dev = .timid = 8, .timtype = TIMTYPE_TIM8, .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, - .irq = PULSECOUNT_TIM8_IRQ, + .irq = STM32_IRQ_TIM8UP, .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; @@ -1698,6 +1680,7 @@ static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev) static int pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev) { struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; + return pulsecount_ll_shutdown((struct pulsecount_lowerhalf_s *) pulse->timer); } @@ -1736,6 +1719,7 @@ static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, static int pulsecount_stop(struct pulsecount_lowerhalf_s *dev) { struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; + return pulsecount_ll_stop((struct pulsecount_lowerhalf_s *)pulse->timer); } @@ -1743,6 +1727,7 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, unsigned long arg) { struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; + return pulsecount_ll_ioctl((struct pulsecount_lowerhalf_s *)pulse->timer, cmd, arg); } diff --git a/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c b/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c index e88ff33418d..bd9e47f3dbc 100644 --- a/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c +++ b/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c @@ -285,7 +285,7 @@ static const struct qe_ops_s g_qecallbacks = static const struct stm32_qeconfig_s g_tim1config = { .timid = 1, - .irq = STM32_IRQ_TIM1_BRK, + .irq = STM32_IRQ_TIM1UP, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM1_BITWIDTH, #endif diff --git a/arch/arm/src/common/stm32/stm32_tim_m0_v1.c b/arch/arm/src/common/stm32/stm32_tim_m0_v1.c index 58255a4955e..2a42c738df6 100644 --- a/arch/arm/src/common/stm32/stm32_tim_m0_v1.c +++ b/arch/arm/src/common/stm32/stm32_tim_m0_v1.c @@ -791,7 +791,7 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1_BRK; + vectorno = STM32_IRQ_TIM1UP; break; #endif #ifdef CONFIG_STM32_TIM2 diff --git a/arch/arm/src/stm32h5/stm32_tim.c b/arch/arm/src/stm32h5/stm32_tim.c index 2be01522413..e49d2457793 100644 --- a/arch/arm/src/stm32h5/stm32_tim.c +++ b/arch/arm/src/stm32h5/stm32_tim.c @@ -742,7 +742,7 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1_UP; + vectorno = STM32_IRQ_TIM1UP; break; #endif #ifdef CONFIG_STM32_TIM2 @@ -777,7 +777,7 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, #endif #ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8_UP; + vectorno = STM32_IRQ_TIM8UP; break; #endif #ifdef CONFIG_STM32_TIM12
