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commit 75fcb2cd09d2347625f86eba4dbbd22ae25a241b Author: raiden00pl <[email protected]> AuthorDate: Sat Oct 10 13:57:43 2026 +0200 arch/arm/src/common/stm32: drop core prefix from timer IP names The timer IP versions are about to be selected by Cortex-M7 (F7/H7), Cortex-M33 (H5/L5/U5/C5/U3) and Cortex-M55 (N6) families. An IP version names the silicon only and must not encode the CPU core it sits next to, so drop the m3m4 prefix before extending them: - STM32_HAVE_IP_TIMERS_M3M4_V1 -> STM32_HAVE_IP_TIMERS_V1 - STM32_HAVE_IP_TIMERS_M3M4_V2 -> STM32_HAVE_IP_TIMERS_V2 - STM32_HAVE_IP_TIMERS_M3M4_V3 -> STM32_HAVE_IP_TIMERS_V3 STM32_HAVE_IP_TIMERS_M0_V1 is used by Cortex-M0 families only and keeps its prefix. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- Documentation/guides/chip-specific/stm32_ports.rst | 21 +++++------ arch/arm/src/common/stm32/Kconfig.have | 10 +++--- arch/arm/src/common/stm32/Kconfig.tim | 42 +++++++++++----------- arch/arm/src/common/stm32/hardware/stm32_tim.h | 18 +++++----- .../arm/src/common/stm32/hardware/stm32_tim_v1v2.h | 4 +-- arch/arm/src/common/stm32/stm32_pwm.h | 6 ++-- arch/arm/src/common/stm32/stm32_tim.h | 6 ++-- arch/arm/src/stm32f1/Kconfig | 2 +- arch/arm/src/stm32f2/Kconfig | 2 +- arch/arm/src/stm32f3/Kconfig | 6 ++-- arch/arm/src/stm32f4/Kconfig | 2 +- arch/arm/src/stm32g4/Kconfig | 2 +- arch/arm/src/stm32l1/Kconfig | 2 +- arch/arm/src/stm32wb/Kconfig | 12 +++---- 14 files changed, 68 insertions(+), 67 deletions(-) diff --git a/Documentation/guides/chip-specific/stm32_ports.rst b/Documentation/guides/chip-specific/stm32_ports.rst index 1ca1430cf3d..7c2a7b8c7b6 100644 --- a/Documentation/guides/chip-specific/stm32_ports.rst +++ b/Documentation/guides/chip-specific/stm32_ports.rst @@ -206,9 +206,9 @@ keeps the same programming model: IP core Selector Families ========== ================================= ================================= M0_V1 ``STM32_HAVE_IP_TIMERS_M0_V1`` Cortex-M0 (C0, F0, G0, L0, U0) -M3M4_V1 ``STM32_HAVE_IP_TIMERS_M3M4_V1`` F1, F2, F4, L1, F37x -M3M4_V2 ``STM32_HAVE_IP_TIMERS_M3M4_V2`` F30x, F33x, WB -M3M4_V3 ``STM32_HAVE_IP_TIMERS_M3M4_V3`` G4 +V1 ``STM32_HAVE_IP_TIMERS_V1`` F1, F2, F4, L1, F37x +V2 ``STM32_HAVE_IP_TIMERS_V2`` F30x, F33x, WB +V3 ``STM32_HAVE_IP_TIMERS_V3`` G4 ========== ================================= ================================= Families with their own timer register header (F7, H7, H5, L4, L5, U5, WL5) @@ -218,7 +218,7 @@ common driver. The one functional difference that matters to a generic timer user is the **counter width**. Every timer is 16-bit except TIM2 and TIM5, which are 32-bit on most families. Because counter width does not follow the IP-core -version (e.g. TIM2 is 16-bit on F1 but 32-bit on F4, both ``M3M4_V1``), it is +version (e.g. TIM2 is 16-bit on F1 but 32-bit on F4, both ``V1``), it is carried by its own capability flags rather than by the IP selector or a chip ``#ifdef``: @@ -1039,16 +1039,17 @@ of a peripheral on a given core is ``V1``. - M0: ``CONFIG_STM32_HAVE_IP_GPIO_M0_V1``, ``CONFIG_STM32_HAVE_IP_ADC_M0_V1`` - M3/M4: ``CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1``, - ``CONFIG_STM32_HAVE_IP_ADC_M3M4_V1``, ``CONFIG_STM32_HAVE_IP_ADC_M3M4_V2``, - ``CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1``, ``CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2``, - ``CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3`` + ``CONFIG_STM32_HAVE_IP_ADC_M3M4_V1``, ``CONFIG_STM32_HAVE_IP_ADC_M3M4_V2`` - M33: ``CONFIG_STM32_HAVE_IP_GPIO_M33_V1``, ``CONFIG_STM32_HAVE_IP_EXTI_M33_V1``, and ``CONFIG_STM32_HAVE_IP_USART_M33_V3`` +- No core prefix (used by several core classes): + ``CONFIG_STM32_HAVE_IP_TIMERS_V1``, ``CONFIG_STM32_HAVE_IP_TIMERS_V2``, + ``CONFIG_STM32_HAVE_IP_TIMERS_V3`` -Note that in the future the core prefix may be dropped and a single -version number space used across all cores. For now the core prefix is -kept to make migration of families into common code simpler. +The core prefix is dropped once an IP is used by more than one core +class. Until then it is kept to make migration of families into common +code simpler. Common STM32 files should follow these rules: diff --git a/arch/arm/src/common/stm32/Kconfig.have b/arch/arm/src/common/stm32/Kconfig.have index fcf89f261a0..cf087e2149b 100644 --- a/arch/arm/src/common/stm32/Kconfig.have +++ b/arch/arm/src/common/stm32/Kconfig.have @@ -903,11 +903,11 @@ config STM32_HAVE_TIM_PWM_STM32PWM config STM32_HAVE_TIM_PWM_CHMODE_EXTENDED bool - default y if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + default y if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 config STM32_HAVE_TIM_PWM_CHMODE_LEGACY bool - default y if STM32_HAVE_IP_TIMERS && !STM32_HAVE_IP_TIMERS_M3M4_V2 + default y if STM32_HAVE_IP_TIMERS && !STM32_HAVE_IP_TIMERS_V2 config STM32_HAVE_TIM_PWM_CHMODE_LIMITED bool @@ -948,15 +948,15 @@ config STM32_HAVE_LPTIM_CHANNEL config STM32_HAVE_IP_TIMERS bool -config STM32_HAVE_IP_TIMERS_M3M4_V1 +config STM32_HAVE_IP_TIMERS_V1 bool select STM32_HAVE_IP_TIMERS -config STM32_HAVE_IP_TIMERS_M3M4_V2 +config STM32_HAVE_IP_TIMERS_V2 bool select STM32_HAVE_IP_TIMERS -config STM32_HAVE_IP_TIMERS_M3M4_V3 +config STM32_HAVE_IP_TIMERS_V3 bool select STM32_HAVE_IP_TIMERS diff --git a/arch/arm/src/common/stm32/Kconfig.tim b/arch/arm/src/common/stm32/Kconfig.tim index b8e7852a920..4dd1c3e9294 100644 --- a/arch/arm/src/common/stm32/Kconfig.tim +++ b/arch/arm/src/common/stm32/Kconfig.tim @@ -1209,7 +1209,7 @@ config STM32_TIM1_CH4OUT config STM32_TIM1_CHANNEL5 bool "TIM1 Channel 5 (internal)" depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 ---help--- Enables channel 5 (not available externally) @@ -1232,7 +1232,7 @@ config STM32_TIM1_CH5OUT config STM32_TIM1_CHANNEL6 bool "TIM1 Channel 6 (internal)" depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 ---help--- Enables channel 6 (not available externally) @@ -2022,7 +2022,7 @@ config STM32_TIM8_CH4OUT config STM32_TIM8_CHANNEL5 bool "TIM8 Channel 5 (internal)" depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 ---help--- Enables channel 5 (not available externally) @@ -2045,7 +2045,7 @@ config STM32_TIM8_CH5OUT config STM32_TIM8_CHANNEL6 bool "TIM8 Channel 6 (internal)" depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 ---help--- Enables channel 6 (not available externally) @@ -2108,7 +2108,7 @@ config STM32_TIM9_CH1MODE int "TIM9 Channel 1 Mode" depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1 default 6 - range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2 range 0 9 if ARCH_CHIP_STM32F7 range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY ---help--- @@ -2131,7 +2131,7 @@ config STM32_TIM9_CH2MODE int "TIM9 Channel 2 Mode" depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2 default 6 - range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2 range 0 9 if ARCH_CHIP_STM32F7 range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY ---help--- @@ -2158,7 +2158,7 @@ config STM32_TIM9_CHMODE int "TIM9 Channel Mode" depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) default 6 - range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2 range 0 9 if ARCH_CHIP_STM32F7 range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY ---help--- @@ -2186,7 +2186,7 @@ config STM32_TIM10_CH1MODE int "TIM10 Channel 1 Mode" depends on STM32_TIM10_PWM && STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1 default 6 - range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2 range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 ---help--- Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. @@ -2212,7 +2212,7 @@ config STM32_TIM10_CHMODE int "TIM10 Channel Mode" depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) default 6 - range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2 range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 ---help--- Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. @@ -2239,7 +2239,7 @@ config STM32_TIM11_CH1MODE int "TIM11 Channel 1 Mode" depends on STM32_TIM11_PWM && STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1 default 6 - range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2 range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 ---help--- Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. @@ -2265,7 +2265,7 @@ config STM32_TIM11_CHMODE int "TIM11 Channel Mode" depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) default 6 - range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2 range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 ---help--- Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. @@ -2292,7 +2292,7 @@ config STM32_TIM12_CH1MODE int "TIM12 Channel 1 Mode" depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1 default 6 - range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 range 0 9 if ARCH_CHIP_STM32F7 range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY ---help--- @@ -2315,7 +2315,7 @@ config STM32_TIM12_CH2MODE int "TIM12 Channel 2 Mode" depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2 default 6 - range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 range 0 9 if ARCH_CHIP_STM32F7 range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY ---help--- @@ -2342,7 +2342,7 @@ config STM32_TIM12_CHMODE int "TIM12 Channel Mode" depends on STM32_TIM12_PWM && !STM32_PWM_MULTICHAN default 6 - range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 range 0 9 if ARCH_CHIP_STM32F7 range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY ---help--- @@ -2370,7 +2370,7 @@ config STM32_TIM13_CH1MODE int "TIM13 Channel 1 Mode" depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1 default 6 - range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 ---help--- Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. @@ -2396,7 +2396,7 @@ config STM32_TIM13_CHMODE int "TIM13 Channel Mode" depends on STM32_TIM13_PWM && !STM32_PWM_MULTICHAN default 6 - range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 ---help--- Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. @@ -2424,7 +2424,7 @@ config STM32_TIM14_CH1MODE depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1 default 0 if STM32_HAVE_IP_TIMERS default 6 - range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 range 0 1 if STM32_HAVE_IP_TIMERS ---help--- @@ -2452,7 +2452,7 @@ config STM32_TIM14_CHMODE depends on STM32_TIM14_PWM && !STM32_PWM_MULTICHAN default 0 if STM32_HAVE_IP_TIMERS default 6 - range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 range 0 1 if STM32_HAVE_IP_TIMERS ---help--- @@ -2508,7 +2508,7 @@ config STM32_TIM15_CH1MODE default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED default 6 range 0 11 if ARCH_CHIP_STM32L4 - range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY range 0 3 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED ---help--- @@ -2541,7 +2541,7 @@ config STM32_TIM15_CH2MODE default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED default 6 range 0 11 if ARCH_CHIP_STM32L4 - range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY range 0 3 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED ---help--- @@ -2575,7 +2575,7 @@ config STM32_TIM15_CHMODE depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED default 6 - range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 + range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_V2) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY range 0 3 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED ---help--- diff --git a/arch/arm/src/common/stm32/hardware/stm32_tim.h b/arch/arm/src/common/stm32/hardware/stm32_tim.h index 4db3706e889..93a8b64d851 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_tim.h +++ b/arch/arm/src/common/stm32/hardware/stm32_tim.h @@ -28,22 +28,22 @@ ****************************************************************************/ #if (defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) + \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) + \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) + \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3)) > 1 + defined(CONFIG_STM32_HAVE_IP_TIMERS_V1) + \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_V2) + \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_V3)) > 1 # error Only one STM32 TIMER IP version must be selected #endif #if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) # include "hardware/stm32_tim_v3_m0.h" -#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_V2) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_V3) -#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_V2) # include "stm32_tim_v1v2.h" -#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_V3) # include "stm32_tim_v3.h" #else # error "STM32 TIMER IP version not specified" diff --git a/arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h b/arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h index 5a80e7f02ef..c21eada29ab 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h +++ b/arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h @@ -42,9 +42,9 @@ * - 4-bit SMS in SMCR register */ -#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_V2) # define HAVE_IP_TIMERS_V2 -#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_V1) # define HAVE_IP_TIMERS_V1 #else # error diff --git a/arch/arm/src/common/stm32/stm32_pwm.h b/arch/arm/src/common/stm32/stm32_pwm.h index c2a9a907897..d25915b6575 100644 --- a/arch/arm/src/common/stm32/stm32_pwm.h +++ b/arch/arm/src/common/stm32/stm32_pwm.h @@ -31,9 +31,9 @@ #if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) # include "stm32_pwm_m0_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_V2) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_V3) # include "stm32_pwm_m3m4_v1v2v3.h" #else # error "Unsupported STM32 PWM" diff --git a/arch/arm/src/common/stm32/stm32_tim.h b/arch/arm/src/common/stm32/stm32_tim.h index 60c26af45ed..a521e9a2691 100644 --- a/arch/arm/src/common/stm32/stm32_tim.h +++ b/arch/arm/src/common/stm32/stm32_tim.h @@ -37,9 +37,9 @@ */ #if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) || \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) + defined(CONFIG_STM32_HAVE_IP_TIMERS_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_V2) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_V3) # include "hardware/stm32_tim.h" #elif defined(CONFIG_ARCH_CHIP_STM32L4) # include "hardware/stm32l4_tim.h" diff --git a/arch/arm/src/stm32f1/Kconfig b/arch/arm/src/stm32f1/Kconfig index 8841965cdf3..179229a4d2b 100644 --- a/arch/arm/src/stm32f1/Kconfig +++ b/arch/arm/src/stm32f1/Kconfig @@ -337,7 +337,7 @@ config STM32_STM32F10XX select STM32_HAVE_IP_SDIO_M3M4_V1 if !STM32F1_CONNECTIVITYLINE && !STM32F1_VALUELINE select STM32_HAVE_IP_SPI_V1 select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_TIMERS_V1 select STM32_HAVE_IP_USART_V1 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS diff --git a/arch/arm/src/stm32f2/Kconfig b/arch/arm/src/stm32f2/Kconfig index f51fa6bde06..787ca89d9bd 100644 --- a/arch/arm/src/stm32f2/Kconfig +++ b/arch/arm/src/stm32f2/Kconfig @@ -166,7 +166,7 @@ config STM32_STM32F20XX select STM32_HAVE_IP_SDIO_M3M4_V1 select STM32_HAVE_IP_SPI_V2 select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_TIMERS_V1 select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM5_32BITS select STM32_HAVE_IP_USART_V2 diff --git a/arch/arm/src/stm32f3/Kconfig b/arch/arm/src/stm32f3/Kconfig index 934130b9514..30e9b38121e 100644 --- a/arch/arm/src/stm32f3/Kconfig +++ b/arch/arm/src/stm32f3/Kconfig @@ -448,7 +448,7 @@ config STM32_STM32F30XX select STM32_HAVE_IP_SDIO_M3M4_V1 select STM32_HAVE_IP_SPI_V3 select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_TIMERS_V2 select STM32_HAVE_TIM2_32BITS select STM32_HAVE_IP_USART_V3 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV @@ -542,7 +542,7 @@ config STM32_STM32F33XX select STM32_HAVE_IP_SDIO_M3M4_V1 select STM32_HAVE_IP_SPI_V3 select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_TIMERS_V2 select STM32_HAVE_TIM2_32BITS select STM32_HAVE_IP_USART_V3 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV @@ -587,7 +587,7 @@ config STM32_STM32F37XX select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_TIMERS_V1 select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM5_32BITS select STM32_HAVE_IP_ADC_M3M4_V1_BASIC diff --git a/arch/arm/src/stm32f4/Kconfig b/arch/arm/src/stm32f4/Kconfig index 1d6991ff050..bdd6536a99d 100644 --- a/arch/arm/src/stm32f4/Kconfig +++ b/arch/arm/src/stm32f4/Kconfig @@ -293,7 +293,7 @@ config STM32_STM32F4XXX select STM32_HAVE_IP_SDIO_M3M4_V1 select STM32_HAVE_IP_SPI_V2 select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_TIMERS_V1 select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM5_32BITS select STM32_HAVE_IP_USART_V2 diff --git a/arch/arm/src/stm32g4/Kconfig b/arch/arm/src/stm32g4/Kconfig index 0d24409442e..75fa0601f55 100644 --- a/arch/arm/src/stm32g4/Kconfig +++ b/arch/arm/src/stm32g4/Kconfig @@ -130,7 +130,7 @@ config STM32_STM32G4XXX select STM32_HAVE_PWR select STM32_HAVE_IP_SPI_V3 select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_IP_TIMERS_M3M4_V3 + select STM32_HAVE_IP_TIMERS_V3 select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM5_32BITS select STM32_HAVE_IP_USART_V4 diff --git a/arch/arm/src/stm32l1/Kconfig b/arch/arm/src/stm32l1/Kconfig index 82680c89c65..04462c26c5e 100644 --- a/arch/arm/src/stm32l1/Kconfig +++ b/arch/arm/src/stm32l1/Kconfig @@ -295,7 +295,7 @@ config STM32_STM32L15XX select STM32_HAVE_IP_SDIO_M3M4_V1 select STM32_HAVE_IP_SPI_V1 select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_TIMERS_V1 select STM32_HAVE_TIM5_32BITS select STM32_HAVE_IP_USART_V2 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV diff --git a/arch/arm/src/stm32wb/Kconfig b/arch/arm/src/stm32wb/Kconfig index 959ca9e59fc..d4b598f5c7d 100644 --- a/arch/arm/src/stm32wb/Kconfig +++ b/arch/arm/src/stm32wb/Kconfig @@ -170,7 +170,7 @@ config STM32_STM32WB10 bool default n select STM32_HAVE_TIM1 - select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_TIMERS_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TSC @@ -180,7 +180,7 @@ config STM32_STM32WB15 bool default n select STM32_HAVE_TIM1 - select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_TIMERS_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TSC @@ -193,7 +193,7 @@ config STM32_STM32WB30 default n select STM32_HAVE_HSI48 select STM32_HAVE_TIM1 - select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_TIMERS_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM16 @@ -205,7 +205,7 @@ config STM32_STM32WB50 default n select STM32_HAVE_HSI48 select STM32_HAVE_TIM1 - select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_TIMERS_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM16 @@ -218,7 +218,7 @@ config STM32_STM32WB35 select STM32_HAVE_HSI48 select STM32_HAVE_DMA2 select STM32_HAVE_TIM1 - select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_TIMERS_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM16 @@ -237,7 +237,7 @@ config STM32_STM32WB55 select STM32_HAVE_HSI48 select STM32_HAVE_DMA2 select STM32_HAVE_TIM1 - select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_TIMERS_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM16
