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commit d3ec3619310de932ca35ce048e37789caaf91297 Author: raiden00pl <[email protected]> AuthorDate: Sat Oct 10 16:24:17 2026 +0200 arch/arm/src/stm32l0: add timer support Select the STM32L0 timers TIM2, TIM3, TIM6 and TIM7 so the common timer drivers can be enabled, and add their input clock definitions to the L0 boards. TIM21 and TIM22 are not supported by the common timer driver. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- arch/arm/src/stm32l0/Kconfig | 4 ++++ boards/arm/stm32l0/b-l072z-lrwan1/include/board.h | 7 +++++++ boards/arm/stm32l0/nucleo-l073rz/include/board.h | 7 +++++++ boards/arm/stm32l0/stm32l0538-disco/include/board.h | 7 +++++++ 4 files changed, 25 insertions(+) diff --git a/arch/arm/src/stm32l0/Kconfig b/arch/arm/src/stm32l0/Kconfig index 4051b06027b..830f05536c6 100644 --- a/arch/arm/src/stm32l0/Kconfig +++ b/arch/arm/src/stm32l0/Kconfig @@ -228,6 +228,10 @@ config STM32_STM32L0 select STM32_HAVE_IP_PWR_M0_V1 select STM32_HAVE_IP_SPI_V1 select STM32_HAVE_IP_TIMERS_M0_V1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 select STM32_HAVE_IP_USART_V3 select STM32_HAVE_IP_WDG_M0_V1 select STM32_HAVE_IP_RNG_M0_V1 if STM32_HAVE_RNG diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/include/board.h b/boards/arm/stm32l0/b-l072z-lrwan1/include/board.h index 2029f595402..bfa31b69e7c 100644 --- a/boards/arm/stm32l0/b-l072z-lrwan1/include/board.h +++ b/boards/arm/stm32l0/b-l072z-lrwan1/include/board.h @@ -85,6 +85,13 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) +/* APB1 timers 2, 3, 6 and 7 will receive PCLK1 * 2 */ + +#define STM32_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) + /* 48MHz clock configuration */ #if defined(CONFIG_STM32_USB) || defined(CONFIG_STM32_RNG) diff --git a/boards/arm/stm32l0/nucleo-l073rz/include/board.h b/boards/arm/stm32l0/nucleo-l073rz/include/board.h index 03398e212d2..1cecadcde3d 100644 --- a/boards/arm/stm32l0/nucleo-l073rz/include/board.h +++ b/boards/arm/stm32l0/nucleo-l073rz/include/board.h @@ -86,6 +86,13 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) +/* APB1 timers 2, 3, 6 and 7 will receive PCLK1 * 2 */ + +#define STM32_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) + /* 48MHz clock configuration */ #if defined(CONFIG_STM32_USB) || defined(CONFIG_STM32_RNG) diff --git a/boards/arm/stm32l0/stm32l0538-disco/include/board.h b/boards/arm/stm32l0/stm32l0538-disco/include/board.h index f1ba04878c6..7ce360de4fc 100644 --- a/boards/arm/stm32l0/stm32l0538-disco/include/board.h +++ b/boards/arm/stm32l0/stm32l0538-disco/include/board.h @@ -81,6 +81,13 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) +/* APB1 timers 2, 3, 6 and 7 will receive PCLK1 * 2 */ + +#define STM32_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) + /* 48MHz clock configuration */ #if defined(CONFIG_STM32_USB) || defined(CONFIG_STM32_RNG)
