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commit 482fa3a9f106d8b25b17aeb977459a10d95e1382 Author: raiden00pl <[email protected]> AuthorDate: Sat Oct 10 18:18:02 2026 +0200 arch/arm/src/stm32h7: fix the timer build on H7RS The common timer driver could not be built for STM32H7RS: - The H7 I2C and SPI register header dispatchers had no H7RS case and stopped the build. The H7RS I2C registers match H7x3; SPI register definitions for H7RS are not provided. - The legacy H7 RCC aliases were missing the TIM12-TIM14 enable bits and the timer reset bits. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- arch/arm/src/stm32h7/hardware/stm32_i2c.h | 2 ++ arch/arm/src/stm32h7/hardware/stm32_spi.h | 2 ++ arch/arm/src/stm32h7/hardware/stm32h7rsxx_rcc.h | 12 ++++++++++++ 3 files changed, 16 insertions(+) diff --git a/arch/arm/src/stm32h7/hardware/stm32_i2c.h b/arch/arm/src/stm32h7/hardware/stm32_i2c.h index e9b47c45689..18714f60621 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32h7/hardware/stm32_i2c.h @@ -40,6 +40,8 @@ # include "hardware/stm32h7x3xx_i2c.h" #elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_i2c.h" +#elif defined(CONFIG_STM32_STM32H7RSXX) +# include "hardware/stm32h7x3xx_i2c.h" #else # error "Unsupported STM32 H7 sub family" #endif diff --git a/arch/arm/src/stm32h7/hardware/stm32_spi.h b/arch/arm/src/stm32h7/hardware/stm32_spi.h index f342cc3ea35..7bbeb18ab0b 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_spi.h +++ b/arch/arm/src/stm32h7/hardware/stm32_spi.h @@ -40,6 +40,8 @@ # include "hardware/stm32h7x3xx_spi.h" #elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_spi.h" +#elif defined(CONFIG_STM32_STM32H7RSXX) +/* SPI register definitions are not provided for H7RS */ #else # error "Unsupported STM32 H7 sub family" #endif diff --git a/arch/arm/src/stm32h7/hardware/stm32h7rsxx_rcc.h b/arch/arm/src/stm32h7/hardware/stm32h7rsxx_rcc.h index a94737d9260..7e5726e8469 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7rsxx_rcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7rsxx_rcc.h @@ -961,6 +961,9 @@ #define RCC_APB1LENR_TIM5EN RCC_APB1ENR1_TIM5EN #define RCC_APB1LENR_TIM6EN RCC_APB1ENR1_TIM6EN #define RCC_APB1LENR_TIM7EN RCC_APB1ENR1_TIM7EN +#define RCC_APB1LENR_TIM12EN RCC_APB1ENR1_TIM12EN +#define RCC_APB1LENR_TIM13EN RCC_APB1ENR1_TIM13EN +#define RCC_APB1LENR_TIM14EN RCC_APB1ENR1_TIM14EN #define RCC_APB1LENR_LPTIM1EN RCC_APB1ENR1_LPTIM1EN #define RCC_APB1LENR_SPI2EN RCC_APB1ENR1_SPI2EN #define RCC_APB1LENR_SPI3EN RCC_APB1ENR1_SPI3EN @@ -973,6 +976,15 @@ #define RCC_APB1LENR_I2C3EN RCC_APB1ENR1_I2C3EN #define RCC_APB1LENR_UART7EN RCC_APB1ENR1_UART7EN #define RCC_APB1LENR_UART8EN RCC_APB1ENR1_UART8EN +#define RCC_APB1LRSTR_TIM2RST RCC_APB1RSTR1_TIM2RST +#define RCC_APB1LRSTR_TIM3RST RCC_APB1RSTR1_TIM3RST +#define RCC_APB1LRSTR_TIM4RST RCC_APB1RSTR1_TIM4RST +#define RCC_APB1LRSTR_TIM5RST RCC_APB1RSTR1_TIM5RST +#define RCC_APB1LRSTR_TIM6RST RCC_APB1RSTR1_TIM6RST +#define RCC_APB1LRSTR_TIM7RST RCC_APB1RSTR1_TIM7RST +#define RCC_APB1LRSTR_TIM12RST RCC_APB1RSTR1_TIM12RST +#define RCC_APB1LRSTR_TIM13RST RCC_APB1RSTR1_TIM13RST +#define RCC_APB1LRSTR_TIM14RST RCC_APB1RSTR1_TIM14RST #define RCC_APB1LRSTR_I2C1RST RCC_APB1RSTR1_I2C1_I3C1RST #define RCC_APB1LRSTR_I2C2RST RCC_APB1RSTR1_I2C2RST #define RCC_APB1LRSTR_I2C3RST RCC_APB1RSTR1_I2C3RST
