This is an automated email from the ASF dual-hosted git repository. acassis pushed a commit to branch master in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit a2ee3cff954539521dda8dba174aceb3813d7830 Author: raiden00pl <[email protected]> AuthorDate: Sat Oct 10 13:40:14 2026 +0200 arch/arm/src/stm32n6: add timer support Hook STM32N6 into the common STM32 build and select its timers and the timer register layout it shares with G4 (STM32_HAVE_IP_TIMERS_V3), so the common timer drivers can be used. TIM2 and TIM5 are 32-bit. - Add the timer RCC enable, reset and Sleep-mode enable bits, the APB1L/APB2 reset registers, the TIM9-14 and TIM18 base addresses and the timer counts, and a hardware/stm32_rcc.h like the other families. - Keep the timer clocks running in Sleep mode (WFI). The N6 Sleep-mode enable bits reset to 0, so the timers stopped whenever the CPU idled. - TIM10 and TIM11 are on APB1 on N6, so their RCC bus is selected from the RCC bit definitions like TIM12 and TIM14. - The N6 LSI ready flag is in RCC_SR, not in the register with LSION. - Add the STM32_TIMn_CLKIN definitions to the N6 boards. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- Documentation/guides/chip-specific/stm32_ports.rst | 4 +- arch/arm/include/stm32n6/chip.h | 2 + arch/arm/src/common/stm32/stm32_lsi.c | 14 +++- arch/arm/src/common/stm32/stm32_tim_clk.h | 41 ++++++++---- arch/arm/src/stm32n6/CMakeLists.txt | 2 + arch/arm/src/stm32n6/Kconfig | 20 ++++++ arch/arm/src/stm32n6/Make.defs | 1 + arch/arm/src/stm32n6/hardware/stm32_rcc.h | 36 ++++++++++ .../src/stm32n6/hardware/stm32n6xxx_memorymap.h | 7 ++ arch/arm/src/stm32n6/hardware/stm32n6xxx_rcc.h | 76 ++++++++++++++++++++++ arch/arm/src/stm32n6/stm32_start.c | 4 ++ boards/arm/stm32n6/nucleo-n657x0-q/include/board.h | 18 +++++ boards/arm/stm32n6/stm32n6570-dk/include/board.h | 18 +++++ 13 files changed, 227 insertions(+), 16 deletions(-) diff --git a/Documentation/guides/chip-specific/stm32_ports.rst b/Documentation/guides/chip-specific/stm32_ports.rst index 5d066fec493..271b42bc711 100644 --- a/Documentation/guides/chip-specific/stm32_ports.rst +++ b/Documentation/guides/chip-specific/stm32_ports.rst @@ -208,7 +208,7 @@ IP core Selector Families M0_V1 ``STM32_HAVE_IP_TIMERS_M0_V1`` Cortex-M0 (C0, F0, G0, L0, U0) V1 ``STM32_HAVE_IP_TIMERS_V1`` F1, F2, F4, L1, F37x V2 ``STM32_HAVE_IP_TIMERS_V2`` F30x, F33x, F7, H7, L4, L5, WB, WL5 -V3 ``STM32_HAVE_IP_TIMERS_V3`` C5, G4, H5, H7RS, U3, U5 +V3 ``STM32_HAVE_IP_TIMERS_V3`` C5, G4, H5, H7RS, N6, U3, U5 ========== ================================= ================================= The one functional difference that matters to a generic timer user is the @@ -771,7 +771,7 @@ I2C to be done not supported PWR to be done arch/arm/src/stm32n6/stm32_pwr.c RCC to be done arch/arm/src/stm32n6/stm32_rcc.c SPI/I2S to be done not supported -TIM to be done not supported +TIM v3 arch/arm/src/common/stm32/stm32_tim.c USART/LPUART v4 arch/arm/src/stm32n6/stm32_serial.c USB device not supported XSPI to be done not supported diff --git a/arch/arm/include/stm32n6/chip.h b/arch/arm/include/stm32n6/chip.h index 9c50b19c7c7..3cd2f5186bd 100644 --- a/arch/arm/include/stm32n6/chip.h +++ b/arch/arm/include/stm32n6/chip.h @@ -56,6 +56,8 @@ #define STM32_NPORTS (12) /* GPIO ports A-H (8) + N, O, P, Q (4) */ #define STM32_NUSART (1) /* USART1 */ +#define STM32_NATIM (2) /* TIM1 and TIM8 */ +#define STM32_NBTIM (2) /* TIM6 and TIM7 */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/src/common/stm32/stm32_lsi.c b/arch/arm/src/common/stm32/stm32_lsi.c index cecaa5f9032..19e2062a6a4 100644 --- a/arch/arm/src/common/stm32/stm32_lsi.c +++ b/arch/arm/src/common/stm32/stm32_lsi.c @@ -45,12 +45,18 @@ * - STM32C5 : RCC_RTCCR (LSION/LSIRDY) * - STM32WB : RCC_CSR (LSI1ON/LSI1RDY) * - STM32H5/U5 : RCC_BDCR (LSION/LSIRDY) + * - STM32N6 : RCC_CR (LSION), RCC_SR (LSIRDY) * * A single driver therefore serves all of them, selecting the register with * the preprocessor below. */ -#if defined(CONFIG_ARCH_CHIP_STM32C5) +#if defined(CONFIG_ARCH_CHIP_STM32N6) +# define STM32_RCC_LSI_REG STM32_RCC_CR +# define STM32_RCC_LSIRDY_REG STM32_RCC_SR +# define RCC_LSI_LSION RCC_CR_LSION +# define RCC_LSI_LSIRDY RCC_SR_LSIRDY +#elif defined(CONFIG_ARCH_CHIP_STM32C5) # define STM32_RCC_LSI_REG STM32_RCC_RTCCR # define RCC_LSI_LSION RCC_RTCCR_LSION # define RCC_LSI_LSIRDY RCC_RTCCR_LSIRDY @@ -73,6 +79,10 @@ # define RCC_LSI_LSIRDY RCC_CSR_LSIRDY #endif +#ifndef STM32_RCC_LSIRDY_REG +# define STM32_RCC_LSIRDY_REG STM32_RCC_LSI_REG +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -104,7 +114,7 @@ void stm32_rcc_enablelsi(void) /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32_RCC_LSI_REG) & RCC_LSI_LSIRDY) == 0); + while ((getreg32(STM32_RCC_LSIRDY_REG) & RCC_LSI_LSIRDY) == 0); #ifdef CONFIG_STM32_HAVE_IP_PWR_M33_V1 /* Disable backup domain access */ diff --git a/arch/arm/src/common/stm32/stm32_tim_clk.h b/arch/arm/src/common/stm32/stm32_tim_clk.h index f134f9810dc..39cfe888d3b 100644 --- a/arch/arm/src/common/stm32/stm32_tim_clk.h +++ b/arch/arm/src/common/stm32/stm32_tim_clk.h @@ -37,10 +37,11 @@ /* RCC clock-enable and reset aliases for the common timer drivers. * - * TIM1, TIM8, TIM9-11 and TIM15-17 are on APB2, TIM2-7 and TIM13 are on - * APB1. TIM12 and TIM14 are on APB2 on some families, which is detected - * from the RCC bit definitions. The APB1 register names differ between - * families and are selected from the RCC registers the family defines. + * TIM1, TIM8, TIM9 and TIM15-17 are on APB2, TIM2-7 and TIM13 are on + * APB1. TIM10-12 and TIM14 are on APB2 or APB1 depending on the family, + * which is detected from the RCC bit definitions. The APB1 register + * names differ between families and are selected from the RCC registers + * the family defines. * The timer input clock is provided by each board as STM32_TIMn_CLKIN. */ @@ -73,14 +74,6 @@ #define STM32_RCC_TIM9_EN RCC_APB2ENR_TIM9EN #define STM32_RCC_TIM9_RST_REG STM32_RCC_APB2RSTR #define STM32_RCC_TIM9_RST RCC_APB2RSTR_TIM9RST -#define STM32_RCC_TIM10_EN_REG STM32_RCC_APB2ENR -#define STM32_RCC_TIM10_EN RCC_APB2ENR_TIM10EN -#define STM32_RCC_TIM10_RST_REG STM32_RCC_APB2RSTR -#define STM32_RCC_TIM10_RST RCC_APB2RSTR_TIM10RST -#define STM32_RCC_TIM11_EN_REG STM32_RCC_APB2ENR -#define STM32_RCC_TIM11_EN RCC_APB2ENR_TIM11EN -#define STM32_RCC_TIM11_RST_REG STM32_RCC_APB2RSTR -#define STM32_RCC_TIM11_RST RCC_APB2RSTR_TIM11RST #define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR #define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN #define STM32_RCC_TIM15_RST_REG STM32_RCC_APB2RSTR @@ -123,6 +116,30 @@ #define STM32_RCC_TIM13_RST_REG STM32_RCC_TIM_APB1RST_REG #define STM32_RCC_TIM13_RST STM32_RCC_TIM_APB1RST(13) +#ifdef RCC_APB2ENR_TIM10EN +# define STM32_RCC_TIM10_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM10_EN RCC_APB2ENR_TIM10EN +# define STM32_RCC_TIM10_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM10_RST RCC_APB2RSTR_TIM10RST +#else +# define STM32_RCC_TIM10_EN_REG STM32_RCC_TIM_APB1EN_REG +# define STM32_RCC_TIM10_EN STM32_RCC_TIM_APB1EN(10) +# define STM32_RCC_TIM10_RST_REG STM32_RCC_TIM_APB1RST_REG +# define STM32_RCC_TIM10_RST STM32_RCC_TIM_APB1RST(10) +#endif + +#ifdef RCC_APB2ENR_TIM11EN +# define STM32_RCC_TIM11_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM11_EN RCC_APB2ENR_TIM11EN +# define STM32_RCC_TIM11_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM11_RST RCC_APB2RSTR_TIM11RST +#else +# define STM32_RCC_TIM11_EN_REG STM32_RCC_TIM_APB1EN_REG +# define STM32_RCC_TIM11_EN STM32_RCC_TIM_APB1EN(11) +# define STM32_RCC_TIM11_RST_REG STM32_RCC_TIM_APB1RST_REG +# define STM32_RCC_TIM11_RST STM32_RCC_TIM_APB1RST(11) +#endif + #ifdef RCC_APB2ENR_TIM12EN # define STM32_RCC_TIM12_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM12_EN RCC_APB2ENR_TIM12EN diff --git a/arch/arm/src/stm32n6/CMakeLists.txt b/arch/arm/src/stm32n6/CMakeLists.txt index cd2b788424d..983b67744f9 100644 --- a/arch/arm/src/stm32n6/CMakeLists.txt +++ b/arch/arm/src/stm32n6/CMakeLists.txt @@ -20,6 +20,8 @@ # # ############################################################################## +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) + set(SRCS) # Required STM32N6 files diff --git a/arch/arm/src/stm32n6/Kconfig b/arch/arm/src/stm32n6/Kconfig index 68d8a1b051e..f405994b59b 100644 --- a/arch/arm/src/stm32n6/Kconfig +++ b/arch/arm/src/stm32n6/Kconfig @@ -10,6 +10,26 @@ comment "STM32N6 Configuration Options" config STM32_N6_PERIPHERALS bool default y + select STM32_HAVE_IP_TIMERS_V3 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_USART1 config STM32_STM32N6XXXX diff --git a/arch/arm/src/stm32n6/Make.defs b/arch/arm/src/stm32n6/Make.defs index 7be078fc1ef..9550e4e64a5 100644 --- a/arch/arm/src/stm32n6/Make.defs +++ b/arch/arm/src/stm32n6/Make.defs @@ -28,6 +28,7 @@ HEAD_ASRC = # Common ARM and Cortex-M55 files (ARMv8-M base) include armv8-m/Make.defs +include common/stm32/Make.defs # Required STM32N6 files diff --git a/arch/arm/src/stm32n6/hardware/stm32_rcc.h b/arch/arm/src/stm32n6/hardware/stm32_rcc.h new file mode 100644 index 00000000000..36a461b5c76 --- /dev/null +++ b/arch/arm/src/stm32n6/hardware/stm32_rcc.h @@ -0,0 +1,36 @@ +/**************************************************************************** + * arch/arm/src/stm32n6/hardware/stm32_rcc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32_RCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" + +#include "hardware/stm32n6xxx_rcc.h" + +#endif /* __ARCH_ARM_SRC_STM32N6_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32n6/hardware/stm32n6xxx_memorymap.h b/arch/arm/src/stm32n6/hardware/stm32n6xxx_memorymap.h index 2911e9d02ab..54b8c441e78 100644 --- a/arch/arm/src/stm32n6/hardware/stm32n6xxx_memorymap.h +++ b/arch/arm/src/stm32n6/hardware/stm32n6xxx_memorymap.h @@ -79,7 +79,12 @@ #define STM32_TIM5_BASE 0x50000c00 #define STM32_TIM6_BASE 0x50001000 #define STM32_TIM7_BASE 0x50001400 +#define STM32_TIM12_BASE 0x50001800 +#define STM32_TIM13_BASE 0x50001c00 +#define STM32_TIM14_BASE 0x50002000 #define STM32_LPTIM1_BASE 0x50002400 +#define STM32_TIM10_BASE 0x50003000 +#define STM32_TIM11_BASE 0x50003400 #define STM32_SPI2_BASE 0x50003800 #define STM32_SPI3_BASE 0x50003c00 #define STM32_USART2_BASE 0x50004400 @@ -97,9 +102,11 @@ #define STM32_USART1_BASE 0x52001000 #define STM32_SPI1_BASE 0x52003000 #define STM32_SPI4_BASE 0x52003400 +#define STM32_TIM18_BASE 0x52003c00 #define STM32_TIM15_BASE 0x52004000 #define STM32_TIM16_BASE 0x52004400 #define STM32_TIM17_BASE 0x52004800 +#define STM32_TIM9_BASE 0x52004c00 #define STM32_SPI5_BASE 0x52005000 /* APB4 peripherals *********************************************************/ diff --git a/arch/arm/src/stm32n6/hardware/stm32n6xxx_rcc.h b/arch/arm/src/stm32n6/hardware/stm32n6xxx_rcc.h index 824af5f379d..39922939fa7 100644 --- a/arch/arm/src/stm32n6/hardware/stm32n6xxx_rcc.h +++ b/arch/arm/src/stm32n6/hardware/stm32n6xxx_rcc.h @@ -48,6 +48,8 @@ #define STM32_RCC_IC6CFGR_OFFSET 0x00d8 /* IC6 configuration register */ #define STM32_RCC_IC11CFGR_OFFSET 0x00ec /* IC11 configuration register */ #define STM32_RCC_CCIPR13_OFFSET 0x0174 /* Peripheral kernel clock select register 13 */ +#define STM32_RCC_APB1LRSTR_OFFSET 0x0224 /* APB1 peripheral reset register 1 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x022c /* APB2 peripheral reset register */ /* Peripheral clock enable / set / clear register offsets. Each enable * register (xxxENR) has a paired set register (xxxENSR) that performs an @@ -98,6 +100,8 @@ #define STM32_RCC_IC6CFGR (STM32_RCC_BASE + STM32_RCC_IC6CFGR_OFFSET) #define STM32_RCC_IC11CFGR (STM32_RCC_BASE + STM32_RCC_IC11CFGR_OFFSET) #define STM32_RCC_CCIPR13 (STM32_RCC_BASE + STM32_RCC_CCIPR13_OFFSET) +#define STM32_RCC_APB1LRSTR (STM32_RCC_BASE + STM32_RCC_APB1LRSTR_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) #define STM32_RCC_DIVENR (STM32_RCC_BASE + STM32_RCC_DIVENR_OFFSET) #define STM32_RCC_DIVENSR (STM32_RCC_BASE + STM32_RCC_DIVENSR_OFFSET) @@ -133,11 +137,13 @@ #define RCC_CR_PLL1ON (1 << 8) /* Bit 8: PLL1 enable */ #define RCC_CR_HSION (1 << 3) /* Bit 3: HSI enable */ +#define RCC_CR_LSION (1 << 0) /* Bit 0: LSI enable */ /* Clock status register */ #define RCC_SR_PLL1RDY (1 << 8) /* Bit 8: PLL1 clock ready */ #define RCC_SR_HSIRDY (1 << 3) /* Bit 3: HSI clock ready */ +#define RCC_SR_LSIRDY (1 << 0) /* Bit 0: LSI clock ready */ /* Clock configuration register 1. SYSSW = 0b11 selects three IC dividers * (IC2 for SYSCLK, IC6 for AHB, IC11 for APB) -- the SVD names this state @@ -241,11 +247,52 @@ /* APB1 peripheral clock enable register 1 */ +#define RCC_APB1LENR_TIM11EN (1 << 13) /* Bit 13: TIM11 enable */ +#define RCC_APB1LENR_TIM10EN (1 << 12) /* Bit 12: TIM10 enable */ +#define RCC_APB1LENR_TIM14EN (1 << 8) /* Bit 8: TIM14 enable */ +#define RCC_APB1LENR_TIM13EN (1 << 7) /* Bit 7: TIM13 enable */ +#define RCC_APB1LENR_TIM12EN (1 << 6) /* Bit 6: TIM12 enable */ +#define RCC_APB1LENR_TIM7EN (1 << 5) /* Bit 5: TIM7 enable */ +#define RCC_APB1LENR_TIM6EN (1 << 4) /* Bit 4: TIM6 enable */ +#define RCC_APB1LENR_TIM5EN (1 << 3) /* Bit 3: TIM5 enable */ +#define RCC_APB1LENR_TIM4EN (1 << 2) /* Bit 2: TIM4 enable */ +#define RCC_APB1LENR_TIM3EN (1 << 1) /* Bit 1: TIM3 enable */ #define RCC_APB1LENR_TIM2EN (1 << 0) /* Bit 0: TIM2 enable */ /* APB2 peripheral clock enable register */ +#define RCC_APB2ENR_TIM9EN (1 << 19) /* Bit 19: TIM9 enable */ +#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: TIM17 enable */ +#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: TIM16 enable */ +#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: TIM15 enable */ +#define RCC_APB2ENR_TIM18EN (1 << 15) /* Bit 15: TIM18 enable */ #define RCC_APB2ENR_USART1EN (1 << 4) /* Bit 4: USART1 enable */ +#define RCC_APB2ENR_TIM8EN (1 << 1) /* Bit 1: TIM8 enable */ +#define RCC_APB2ENR_TIM1EN (1 << 0) /* Bit 0: TIM1 enable */ + +/* APB1 peripheral reset register 1 */ + +#define RCC_APB1LRSTR_TIM11RST (1 << 13) /* Bit 13: TIM11 reset */ +#define RCC_APB1LRSTR_TIM10RST (1 << 12) /* Bit 12: TIM10 reset */ +#define RCC_APB1LRSTR_TIM14RST (1 << 8) /* Bit 8: TIM14 reset */ +#define RCC_APB1LRSTR_TIM13RST (1 << 7) /* Bit 7: TIM13 reset */ +#define RCC_APB1LRSTR_TIM12RST (1 << 6) /* Bit 6: TIM12 reset */ +#define RCC_APB1LRSTR_TIM7RST (1 << 5) /* Bit 5: TIM7 reset */ +#define RCC_APB1LRSTR_TIM6RST (1 << 4) /* Bit 4: TIM6 reset */ +#define RCC_APB1LRSTR_TIM5RST (1 << 3) /* Bit 3: TIM5 reset */ +#define RCC_APB1LRSTR_TIM4RST (1 << 2) /* Bit 2: TIM4 reset */ +#define RCC_APB1LRSTR_TIM3RST (1 << 1) /* Bit 1: TIM3 reset */ +#define RCC_APB1LRSTR_TIM2RST (1 << 0) /* Bit 0: TIM2 reset */ + +/* APB2 peripheral reset register */ + +#define RCC_APB2RSTR_TIM9RST (1 << 19) /* Bit 19: TIM9 reset */ +#define RCC_APB2RSTR_TIM17RST (1 << 18) /* Bit 18: TIM17 reset */ +#define RCC_APB2RSTR_TIM16RST (1 << 17) /* Bit 17: TIM16 reset */ +#define RCC_APB2RSTR_TIM15RST (1 << 16) /* Bit 16: TIM15 reset */ +#define RCC_APB2RSTR_TIM18RST (1 << 15) /* Bit 15: TIM18 reset */ +#define RCC_APB2RSTR_TIM8RST (1 << 1) /* Bit 1: TIM8 reset */ +#define RCC_APB2RSTR_TIM1RST (1 << 0) /* Bit 0: TIM1 reset */ /* APB4 peripheral clock enable register 2 */ @@ -273,11 +320,40 @@ /* APB1 peripheral clock enable in Sleep mode (register 1) */ +#define RCC_APB1LLPENR_TIM11LPEN (1 << 13) /* Bit 13: TIM11 enable in CSLEEP */ +#define RCC_APB1LLPENR_TIM10LPEN (1 << 12) /* Bit 12: TIM10 enable in CSLEEP */ +#define RCC_APB1LLPENR_TIM14LPEN (1 << 8) /* Bit 8: TIM14 enable in CSLEEP */ +#define RCC_APB1LLPENR_TIM13LPEN (1 << 7) /* Bit 7: TIM13 enable in CSLEEP */ +#define RCC_APB1LLPENR_TIM12LPEN (1 << 6) /* Bit 6: TIM12 enable in CSLEEP */ +#define RCC_APB1LLPENR_TIM7LPEN (1 << 5) /* Bit 5: TIM7 enable in CSLEEP */ +#define RCC_APB1LLPENR_TIM6LPEN (1 << 4) /* Bit 4: TIM6 enable in CSLEEP */ +#define RCC_APB1LLPENR_TIM5LPEN (1 << 3) /* Bit 3: TIM5 enable in CSLEEP */ +#define RCC_APB1LLPENR_TIM4LPEN (1 << 2) /* Bit 2: TIM4 enable in CSLEEP */ +#define RCC_APB1LLPENR_TIM3LPEN (1 << 1) /* Bit 1: TIM3 enable in CSLEEP */ #define RCC_APB1LLPENR_TIM2LPEN (1 << 0) /* Bit 0: TIM2 enable in CSLEEP */ +#define RCC_APB1LLPENR_ALLTIM (RCC_APB1LLPENR_TIM2LPEN | RCC_APB1LLPENR_TIM3LPEN | \ + RCC_APB1LLPENR_TIM4LPEN | RCC_APB1LLPENR_TIM5LPEN | \ + RCC_APB1LLPENR_TIM6LPEN | RCC_APB1LLPENR_TIM7LPEN | \ + RCC_APB1LLPENR_TIM10LPEN | RCC_APB1LLPENR_TIM11LPEN | \ + RCC_APB1LLPENR_TIM12LPEN | RCC_APB1LLPENR_TIM13LPEN | \ + RCC_APB1LLPENR_TIM14LPEN) + /* APB2 peripheral clock enable in Sleep mode */ +#define RCC_APB2LPENR_TIM9LPEN (1 << 19) /* Bit 19: TIM9 enable in CSLEEP */ +#define RCC_APB2LPENR_TIM17LPEN (1 << 18) /* Bit 18: TIM17 enable in CSLEEP */ +#define RCC_APB2LPENR_TIM16LPEN (1 << 17) /* Bit 17: TIM16 enable in CSLEEP */ +#define RCC_APB2LPENR_TIM15LPEN (1 << 16) /* Bit 16: TIM15 enable in CSLEEP */ +#define RCC_APB2LPENR_TIM18LPEN (1 << 15) /* Bit 15: TIM18 enable in CSLEEP */ #define RCC_APB2LPENR_USART1LPEN (1 << 4) /* Bit 4: USART1 enable in CSLEEP */ +#define RCC_APB2LPENR_TIM8LPEN (1 << 1) /* Bit 1: TIM8 enable in CSLEEP */ +#define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* Bit 0: TIM1 enable in CSLEEP */ + +#define RCC_APB2LPENR_ALLTIM (RCC_APB2LPENR_TIM1LPEN | RCC_APB2LPENR_TIM8LPEN | \ + RCC_APB2LPENR_TIM9LPEN | RCC_APB2LPENR_TIM15LPEN | \ + RCC_APB2LPENR_TIM16LPEN | RCC_APB2LPENR_TIM17LPEN | \ + RCC_APB2LPENR_TIM18LPEN) /* Peripheral kernel clock select register 13 */ diff --git a/arch/arm/src/stm32n6/stm32_start.c b/arch/arm/src/stm32n6/stm32_start.c index 7c7c50bd238..a5c2029652c 100644 --- a/arch/arm/src/stm32n6/stm32_start.c +++ b/arch/arm/src/stm32n6/stm32_start.c @@ -226,6 +226,10 @@ void __start_c(void) #ifdef CONFIG_STM32_USART1 putreg32(RCC_APB2LPENR_USART1LPEN, STM32_RCC_APB2LPENSR); #endif +#ifdef CONFIG_STM32_TIM + putreg32(RCC_APB1LLPENR_ALLTIM, STM32_RCC_APB1LLPENSR); + putreg32(RCC_APB2LPENR_ALLTIM, STM32_RCC_APB2LPENSR); +#endif /* Mark the board's I/O voltage domains as supply-valid before any GPIO * pad is driven. The mask of PWR_SVMCR3_* bits is board-specific and diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/include/board.h b/boards/arm/stm32n6/nucleo-n657x0-q/include/board.h index 997a4137f55..ccbfa4e4151 100644 --- a/boards/arm/stm32n6/nucleo-n657x0-q/include/board.h +++ b/boards/arm/stm32n6/nucleo-n657x0-q/include/board.h @@ -70,6 +70,24 @@ #define STM32_APB1_TIM_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_APB2_TIM_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_APB2_TIM_FREQUENCY +#define STM32_TIM8_CLKIN STM32_APB2_TIM_FREQUENCY +#define STM32_TIM9_CLKIN STM32_APB2_TIM_FREQUENCY +#define STM32_TIM15_CLKIN STM32_APB2_TIM_FREQUENCY +#define STM32_TIM16_CLKIN STM32_APB2_TIM_FREQUENCY +#define STM32_TIM17_CLKIN STM32_APB2_TIM_FREQUENCY +#define STM32_TIM2_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM3_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM4_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM5_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM6_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM7_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM10_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM11_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM12_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM13_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM14_CLKIN STM32_APB1_TIM_FREQUENCY + /* I/O voltage domains ******************************************************/ /* GPIO port E (USART1 TX/RX on PE5/PE6) is on the VddIO2 and VddIO3 diff --git a/boards/arm/stm32n6/stm32n6570-dk/include/board.h b/boards/arm/stm32n6/stm32n6570-dk/include/board.h index bcd57f8d0ee..c64d052ea29 100644 --- a/boards/arm/stm32n6/stm32n6570-dk/include/board.h +++ b/boards/arm/stm32n6/stm32n6570-dk/include/board.h @@ -70,6 +70,24 @@ #define STM32_APB1_TIM_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_APB2_TIM_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_APB2_TIM_FREQUENCY +#define STM32_TIM8_CLKIN STM32_APB2_TIM_FREQUENCY +#define STM32_TIM9_CLKIN STM32_APB2_TIM_FREQUENCY +#define STM32_TIM15_CLKIN STM32_APB2_TIM_FREQUENCY +#define STM32_TIM16_CLKIN STM32_APB2_TIM_FREQUENCY +#define STM32_TIM17_CLKIN STM32_APB2_TIM_FREQUENCY +#define STM32_TIM2_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM3_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM4_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM5_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM6_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM7_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM10_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM11_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM12_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM13_CLKIN STM32_APB1_TIM_FREQUENCY +#define STM32_TIM14_CLKIN STM32_APB1_TIM_FREQUENCY + /* I/O voltage domains ******************************************************/ /* VDDIO2 and VDDIO3 are supplied at 1.8 V on the Discovery kit.
