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commit d6e06b39c8bf135837f69a0e55e20711e0bb4938 Author: raiden00pl <[email protected]> AuthorDate: Sat Oct 10 12:34:48 2026 +0200 arch/arm/src/stm32c5: add timer support Select the STM32C5 timers and the timer register layout they share with G4 (STM32_HAVE_IP_TIMERS_V3), so the common timer drivers can be enabled. TIM2 and TIM5 are 32-bit. The one-shot, free-running and quadrature encoder wrappers are enabled as on the other families with the same timer IP. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- Documentation/guides/chip-specific/stm32_ports.rst | 4 ++-- arch/arm/src/common/stm32/Kconfig.have | 1 + arch/arm/src/common/stm32/Kconfig.tim | 4 ++-- arch/arm/src/stm32c5/Kconfig | 13 +++++++++++++ 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/Documentation/guides/chip-specific/stm32_ports.rst b/Documentation/guides/chip-specific/stm32_ports.rst index 27ec62d06ae..19780a41936 100644 --- a/Documentation/guides/chip-specific/stm32_ports.rst +++ b/Documentation/guides/chip-specific/stm32_ports.rst @@ -208,7 +208,7 @@ IP core Selector Families M0_V1 ``STM32_HAVE_IP_TIMERS_M0_V1`` Cortex-M0 (C0, F0, G0, L0, U0) V1 ``STM32_HAVE_IP_TIMERS_V1`` F1, F2, F4, L1, F37x V2 ``STM32_HAVE_IP_TIMERS_V2`` F30x, F33x, F7, H7, L4, L5, WB, WL5 -V3 ``STM32_HAVE_IP_TIMERS_V3`` G4, H5, H7RS, U5 +V3 ``STM32_HAVE_IP_TIMERS_V3`` C5, G4, H5, H7RS, U5 ========== ================================= ================================= The one functional difference that matters to a generic timer user is the @@ -303,7 +303,7 @@ RTC to be done not supported SBS to be done not supported SPI/I2S to be done not supported TAMP to be done not supported -TIM to be done not supported +TIM v3 arch/arm/src/common/stm32/stm32_tim.c USART/UART M33 v3 arch/arm/src/common/stm32/stm32_serial_m33_v3.c USB_FS FS not supported WWDG to be done not supported diff --git a/arch/arm/src/common/stm32/Kconfig.have b/arch/arm/src/common/stm32/Kconfig.have index c3c58cae6cf..bfc86188a59 100644 --- a/arch/arm/src/common/stm32/Kconfig.have +++ b/arch/arm/src/common/stm32/Kconfig.have @@ -932,6 +932,7 @@ config STM32_HAVE_QENCODER_MAIN bool default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 default y if STM32_COMMON_L4_L5_U5 + default y if ARCH_CHIP_STM32C5 config STM32_HAVE_QENCODER_16BIT bool diff --git a/arch/arm/src/common/stm32/Kconfig.tim b/arch/arm/src/common/stm32/Kconfig.tim index 4dd1c3e9294..0baa3964f0d 100644 --- a/arch/arm/src/common/stm32/Kconfig.tim +++ b/arch/arm/src/common/stm32/Kconfig.tim @@ -1000,7 +1000,7 @@ endchoice config STM32_ONESHOT bool "TIM one-shot wrapper" - depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 || (ARCH_CHIP_STM32C5 && STM32_TIM) default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS ---help--- Enable a wrapper around the low level timer/counter functions to @@ -1008,7 +1008,7 @@ config STM32_ONESHOT config STM32_FREERUN bool "TIM free-running wrapper" - depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 || (ARCH_CHIP_STM32C5 && STM32_TIM) default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS ---help--- Enable a wrapper around the low level timer/counter functions to diff --git a/arch/arm/src/stm32c5/Kconfig b/arch/arm/src/stm32c5/Kconfig index 7413d6acd6f..a13f8e23408 100644 --- a/arch/arm/src/stm32c5/Kconfig +++ b/arch/arm/src/stm32c5/Kconfig @@ -13,6 +13,7 @@ config STM32_C5_PERIPHERALS select ARCH_HAVE_FPU select STM32_HAVE_IP_EXTI_M33_V1 select STM32_HAVE_IP_GPIO_M33_V1 + select STM32_HAVE_IP_TIMERS_V3 select STM32_HAVE_IP_USART_M33_V3 select STM32_HAVE_LPUART1 select STM32_HAVE_UART4 @@ -20,6 +21,18 @@ config STM32_C5_PERIPHERALS select STM32_HAVE_USART1 select STM32_HAVE_USART2 select STM32_HAVE_USART3 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS choice prompt "STM32 C5 Chip Selection"
