This is an automated email from the ASF dual-hosted git repository.

acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git

commit 8836db701dc99eed660b8bfd8b235ba95f148636
Author: raiden00pl <[email protected]>
AuthorDate: Sat Oct 10 16:03:47 2026 +0200

    boards/arm/stm32l1/nucleo-l152re: add timer input clocks
    
    Add the timer input clock definitions so the timers can be enabled on
    this board.
    
    Signed-off-by: raiden00pl <[email protected]>
    Assisted-by: Claude Code
---
 boards/arm/stm32l1/nucleo-l152re/include/board.h | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/boards/arm/stm32l1/nucleo-l152re/include/board.h 
b/boards/arm/stm32l1/nucleo-l152re/include/board.h
index a8e89cabee0..014f2f6ab0f 100644
--- a/boards/arm/stm32l1/nucleo-l152re/include/board.h
+++ b/boards/arm/stm32l1/nucleo-l152re/include/board.h
@@ -125,12 +125,25 @@
 #define STM32_PCLK2_FREQUENCY    STM32_HCLK_FREQUENCY
 #define STM32_APB2_CLKIN         STM32_PCLK2_FREQUENCY
 
+/* APB2 timers 9, 10, and 11 will receive PCLK2. */
+
+#define STM32_TIM9_CLKIN    (STM32_PCLK2_FREQUENCY)
+#define STM32_TIM10_CLKIN   (STM32_PCLK2_FREQUENCY)
+#define STM32_TIM11_CLKIN   (STM32_PCLK2_FREQUENCY)
+
 /* APB1 clock (PCLK1) is HCLK (32MHz) */
 
 #define STM32_RCC_CFGR_PPRE1     RCC_CFGR_PPRE1_HCLK
 #define STM32_PCLK1_FREQUENCY    STM32_HCLK_FREQUENCY
 
-/* TODO: Timers */
+/* APB1 timers 2-7 will receive PCLK1 */
+
+#define STM32_TIM2_CLKIN    (STM32_PCLK1_FREQUENCY)
+#define STM32_TIM3_CLKIN    (STM32_PCLK1_FREQUENCY)
+#define STM32_TIM4_CLKIN    (STM32_PCLK1_FREQUENCY)
+#define STM32_TIM5_CLKIN    (STM32_PCLK1_FREQUENCY)
+#define STM32_TIM6_CLKIN    (STM32_PCLK1_FREQUENCY)
+#define STM32_TIM7_CLKIN    (STM32_PCLK1_FREQUENCY)
 
 /* LED definitions **********************************************************/
 

Reply via email to