xiaoxiang781216 commented on code in PR #5985: URL: https://github.com/apache/incubator-nuttx/pull/5985#discussion_r844912065
########## arch/risc-v/src/common/riscv_macros.S: ########## @@ -128,3 +133,22 @@ REGLOAD x31, REG_X31(\out) /* t6 */ .endm + +#if CONFIG_ARCH_INTERRUPTSTACK > 15 +.macro setintstack tmp0, tmp1 +#ifndef CONFIG_ARCH_USE_SMODE +#if CONFIG_SMP_NCPUS > 1 + csrr \tmp0, mhartid Review Comment: It depends on how hardware/software design and config. In many simple design, hartid match index. If you want to support the index isn't equal to hartid. M mode also need the similar percpu struct. Since how to manage hartid is very hardware specific, that's why both riscv spec and NuttX left the detail to chip specific implementation. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
