pussuw commented on code in PR #5985: URL: https://github.com/apache/incubator-nuttx/pull/5985#discussion_r844920820
########## arch/risc-v/src/common/riscv_macros.S: ########## @@ -128,3 +133,22 @@ REGLOAD x31, REG_X31(\out) /* t6 */ .endm + +#if CONFIG_ARCH_INTERRUPTSTACK > 15 +.macro setintstack tmp0, tmp1 +#ifndef CONFIG_ARCH_USE_SMODE +#if CONFIG_SMP_NCPUS > 1 + csrr \tmp0, mhartid Review Comment: Of course, just something to keep in mind here. Can easily produce strange results. A good example is MPFS, which has 5 harts (SiFive cores). Core 0 is u51 which does not have S-mode, FPU, etc. Cores 1-4 are u54, which have S-mode / FPU. So running SMP on e.g. core0&1 makes handling the code difficult, because the cores have different capabilities ! This is why I run NuttX on core 4. With SMP I would most likely use cores 3 and 4 :) -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
