pussuw commented on code in PR #5985:
URL: https://github.com/apache/incubator-nuttx/pull/5985#discussion_r844952193
##########
arch/risc-v/src/common/riscv_macros.S:
##########
@@ -128,3 +133,22 @@
REGLOAD x31, REG_X31(\out) /* t6 */
.endm
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 15
+.macro setintstack tmp0, tmp1
+#ifndef CONFIG_ARCH_USE_SMODE
+#if CONFIG_SMP_NCPUS > 1
+ csrr \tmp0, mhartid
Review Comment:
I think all (or at least many) risc-v targets use interrupt stack now even
without SMP. This macro will work for them, because setting the interrupt stack
was just:
exception_common:
` la sp, g_intstacktop`
This does not quite work either, because setinstack for mpfs is needed when
1 hart is used (to use the percpu structure):
exception_common:
```
#if CONFIG_SMP_NCPUS > 1
setintstack t0, t1
#else
la sp, g_intstacktop
#endif
```
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