On 28.05.2009 21:04, Alexander Gordeev wrote: > On Thursday 28 May 2009 15:58:16 Carl-Daniel Hailfinger wrote: > >> On 27.05.2009 21:31, Alexander Gordeev wrote: >> >>> I also found the SuperIO pin, which is connected to WE pin of flash: it >>> is pin 71, PSIN/GP45 as I've learned from the datasheet. However, I was >>> only able to find it8712f datasheet which may be a bit different from >>> it8712f-a. You can obtain a foto of the chip from here: >>> http://lvk.cs.msu.su/~lasaine/it8712f-a.png >>> The pin is marked. >>> >> Wow, that's very precise and helpful information. Thanks! >> > > I did my best :) >
Could you also trace the WP# (and TBL#) pin? It seems that my first attempt to guess the right pin was incorrect. >>> I'll be happy to provide any additional information if needed. >>> >> Can you please run >> superiotool -de >> and post the output to the list? That will help me use the correct >> polarity for the write enable routine. >> > > Sure, attached. > Great, thanks! Decode follows. GPIOs: 11(SIO), 12(inverted), 13, 14(SIO), 16(SIO), 17(SIO), 35(pullup), 40(pullup), 53 all SIOs are Input SIO base: 0x0800 That leads me to the assumption that the WP# pin is probably not connected to the SuperIO and the WE# pin may be connected to the SuperIO, but without function. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
