On Fri, 29 May 2009 15:22:33 +0200 Carl-Daniel Hailfinger <[email protected]> wrote:
> On 29.05.2009 14:41, Alexander Gordeev wrote: > > So it seems the right way this time: when WP# is pulled low and > > TBL# is high leads to exactly the same situation as I have. > > > > Yes. I looked at the wrong data sheet when I requested WE# > information. Sorry. Not a problem at all :) > > On Fri, 29 May 2009 13:40:41 +0200 > > Carl-Daniel Hailfinger <[email protected]> wrote: > > > > > >> GPIOs: 11(SIO), 12(inverted), 13, 14(SIO), 16(SIO), 17(SIO), > >> 35(pullup), 40(pullup), 53 > >> all SIOs are Input > >> SIO base: 0x0800 > >> > >> That leads me to the assumption that the WP# pin is probably not > >> connected to the SuperIO and the WE# pin may be connected to the > >> SuperIO, but without function. > >> > > > > I hope WP# is connected... > > > > It may be connected to the southbridge instead. That would make adding > code for it very difficult unless we find someone with specs. I've checked several times and there are no signs that WP or TBL are connected to the SuperIO. So they should be connected to southbridge indeed. And I don't have specs as well. May be I can just cut WP# pin off to disable protection? Thanks for your help! -- Alexander -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
