On Fri, 29 May 2009 13:40:41 +0200 Carl-Daniel Hailfinger <[email protected]> wrote:
> On 28.05.2009 21:04, Alexander Gordeev wrote: > > On Thursday 28 May 2009 15:58:16 Carl-Daniel Hailfinger wrote: > > > >> On 27.05.2009 21:31, Alexander Gordeev wrote: > >> > >>> I also found the SuperIO pin, which is connected to WE pin of > >>> flash: it is pin 71, PSIN/GP45 as I've learned from the > >>> datasheet. However, I was only able to find it8712f datasheet > >>> which may be a bit different from it8712f-a. You can obtain a > >>> foto of the chip from here: > >>> http://lvk.cs.msu.su/~lasaine/it8712f-a.png The pin is marked. > >>> > >> Wow, that's very precise and helpful information. Thanks! > >> > > > > I did my best :) > > > > Could you also trace the WP# (and TBL#) pin? It seems that my first > attempt to guess the right pin was incorrect. Sure! Unfortunately there is a big chance that I won't be able to do this until Monday. An excerpt from the Pm49FL004 datasheet: The Pm49FL002 has a 16 Kbyte top boot block and the Pm49FL004 has a 64 Kbyte top boot block. When work- ing in-system, the memory hardware write protection fea- ture can be activated by two control pins - Top Block Lock (TBL#) and Write Protection (WP#) for both FWH and LPC modes. When TBL# is pulled low (VIL), the boot block is hardware write protected. A sector erase, block erase, or byte program command attempts to erase or program the boot block will be ignored. When WP# is pulled low (VIL), the Block 0 ~ Block 14 of Pm49FL002, or the Block 0 ~ Block 6 of Pm49FL004 (except the boot block) are hardware write protected. Any attemp to erase or program a sector or block within this area will be ig- nored. So it seems the right way this time: when WP# is pulled low and TBL# is high leads to exactly the same situation as I have. > >>> I'll be happy to provide any additional information if needed. > >>> > >> Can you please run > >> superiotool -de > >> and post the output to the list? That will help me use the correct > >> polarity for the write enable routine. > >> > > > > Sure, attached. > > > > Great, thanks! > > Decode follows. > GPIOs: 11(SIO), 12(inverted), 13, 14(SIO), 16(SIO), 17(SIO), > 35(pullup), 40(pullup), 53 > all SIOs are Input > SIO base: 0x0800 > > That leads me to the assumption that the WP# pin is probably not > connected to the SuperIO and the WE# pin may be connected to the > SuperIO, but without function. I hope WP# is connected... -- Alexander -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
