On 08/01/2019 20:50, Rob Clark wrote: > On Tue, Jan 8, 2019 at 3:32 PM Bero Rosenkränzer > <bernhard.rosenkran...@linaro.org> wrote: >> Hi, >> >>> The kernel patch is just about the only really "advanced" thing I had to >>> do. I currently don't really know how I should hack that up to be >>> "consumable in general" (Should we do this all the time on ARM/aarch64 >>> by default? Only on some SoCs/CPUs? Should we create kernel/module >>> parameters to do the above?). >> Given the function it touches is highly arch specific already (it >> comes down to "false on PPC without Coherent Cache, false on >> Loongson3, true for everything else"), I'm pretty sure adding another >> #elif defined(CONFIG_ARM) or so would be acceptable. >> Not sure if there's any SOCs that should be exempted though... >> >> drm_arch_can_wc_memory() seems to be used only in the amdgpu and >> radeon drivers - so SOCs that use Freedreno etc. or boxes with nouveau >> won't be affected (for now). > at least so far adreno is not sitting behind a (real) pci bus.. I > guess the issue on radeon/amdgpu was really about WC + PCI?
it was for me - i just wasn't so sure if blanket returning false for arm (and aar64) was not going to have some unintended victims. i guess given the consensus here. it's worth adding those #ifdefs and submitting a patch upstream. > BR, > -R > >> ttyl >> bero IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ cross-distro mailing list cross-distro@lists.linaro.org https://lists.linaro.org/mailman/listinfo/cross-distro
