I get following message from Altera Quartus compiler:
Info (276007): RAM logic "mem" is uninferred due to asynchronous read logic
File: /home/nyholku/focusscan/top_level.v Line: 18
when I compile/synthesise the Migen memory example:
class MemoryTest(Module):
def __init__(self):
self.specials.mem = Memory(32, 100, init=[5, 18, 32])
p1 = self.mem.get_port(write_capable=True, we_granularity=8)
p2 = self.mem.get_port(has_re=True, clock_domain="rd")
self.specials += p1, p2
self.ios = {p1.adr, p1.dat_r, p1.we, p1.dat_w, p2.adr,
p2.dat_r, p2.re}
if __name__ == "__main__":
memoryTest = MemoryTest()
print(verilog.convert(memoryTest, memoryTest.ios,name="top_level"))
Which generates following (sorry about the missing tabs).
So I gather this means that the synthesiser is not using the FPGA memory (M20k
or MLAB)
and is instead generating memory from LEs.
I'm at loss what I should do here...
wbr Kusti
/* Machine-generated using Migen */
module top_level(
input [6:0] adr,
output [31:0] dat_r,
input [3:0] we,
input [31:0] dat_w,
input [6:0] adr_1,
output [31:0] dat_r_1,
input re,
input rd_clk,
input rd_rst,
input sys_clk,
input sys_rst
);
reg [31:0] mem[0:99];
reg [6:0] memadr;
reg [6:0] memadr_1;
always @(posedge sys_clk) begin
if (we[0])
mem[adr][7:0] <= dat_w[7:0];
if (we[1])
mem[adr][15:8] <= dat_w[15:8];
if (we[2])
mem[adr][23:16] <= dat_w[23:16];
if (we[3])
mem[adr][31:24] <= dat_w[31:24];
memadr <= adr;
end
always @(posedge rd_clk) begin
if (re)
memadr_1 <= adr_1;
end
assign dat_r = mem[memadr];
assign dat_r_1 = mem[memadr_1];
initial begin
$readmemh("mem.init", mem);
end
endmodule
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