On 26/01/2018 12:56, "Sébastien Bourdeauducq" <s...@m-labs.hk> wrote:
On Friday, January 26, 2018 04:54 PM, Kustaa Nyholm wrote:
>Any pointers as to how to approach simulating those 'external' VHDL
>modules in Python/Migen during development without generating
>VHDL and synthesising the code?
>It's not implemented, you'd have to do some non-trivial development
>yourself. You can look at the old (Icarus-based) Migen simulator for
>some ideas on how to interface VPI and Python.
I was looking for guidance/ideas for a less ambitious approach, something
like (sorry to borrow C syntax here):
#ifdef FOR_REAL_HARDWARE
self.specials += Instance("vhdlmodule", ......
#elseif
self.specials += ...migen version of vhdlmodule ...
#endif
I can concoct something myself, just asking if there is experience/best practice
for this situation.
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