> Use Instance, see mor1kx and lm32 in MiSoC.
Ok, got that, thanks, looks straight forward enough. Any pointers as to how to approach simulating those 'external' VHDL modules in Python/Migen during development without generating VHDL and synthesising the code? wbr Kusti _______________________________________________ M-Labs devel mailing list https://ssl.serverraum.org/lists/listinfo/devel
