On Thursday, January 25, 2018 11:40 PM, Kustaa Nyholm wrote:
How can I access some pure Verilog module from Migen ? (So that I can write the critical parts that need to be inferred in pure Verilog)
Use Instance, see mor1kx and lm32 in MiSoC. _______________________________________________ M-Labs devel mailing list https://ssl.serverraum.org/lists/listinfo/devel
