On Friday, January 26, 2018 04:54 PM, Kustaa Nyholm wrote:
Any pointers as to how to approach simulating those 'external' VHDL modules in Python/Migen during development without generating VHDL and synthesising the code?
It's not implemented, you'd have to do some non-trivial development yourself. You can look at the old (Icarus-based) Migen simulator for some ideas on how to interface VPI and Python.
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