Hi, The updated design files are here: http://downloads.qi-hardware.com/hardware/milkymist_one/pcb/rc2/110510/rc2_design.tar.bz2
>The SchLib file is still not up-to-date, and therefore I can't >recompile the LibPkg file in order to run the automated check >to verify that all the footprints on the PCB match those of the library. >Could you update/clean up the libraries? Yes, I was with carelessness. >From 110310, we deleted MilkymistOne.SchLib & .PcbLib, in the schematic editor, "Design->Make Schematic Library"; in the PCB editor, "Design->Make PCB Library"; Recompiled files are under "MilkymistOne" folder. And re-linked 6N138S's library. >"ERROR : More than 500 violations detected, DRC was stopped" ?!?? >Did you run DRC yourself? Can you make sure the DRC rules are up to >date and if needed fix the remaining errors? A large part of those >violations are "matched net length" errors that should not matter, so >the corresponding rule should be changed. >I would like the design to DRC cleanly, or at least not stop after 500 >mostly harmless "violations" and potentially hide more serious ones. Yes, I've checked DRC myself too. That's my fault without up to date and made same DRC rules as RC1. You may already know they are acceptable. After verifying RC1 design files, in 110510, it has been given the same rules as RC1. Check out here. http://en.qi-hardware.com/wiki/Milkymist_One_RC2_Layout_History#20101102 >We should make sure that everything is in sync: >1. recompilation of MilkymistOne.LibPkg should complete without errors >2. after #1 has been solved, in the schematics editor, "Tool->Update >from library" should report no change or error >3. after #2 has been solved, in the schematics editor, "Design->Update >PCB document" should report no important change >4. after #3 has been solved, in the PCB editor, "Tool->Update from PCB >libraries" should report no change or error I tried to follow your instructions above, we encountered another things that we needed to spend the time to face error/changes reported. There are still some unknown knowledges among Altium Designer we don't know. For examples, in RC1 design files, if we followed above 4 steps. Will get error in step1 on parts: 48204-0001, FSMRA2JH and SPC15430 which all say "Could not find port 'SHELL'". Indeed those are not pass AD's internal verification rule but we all know their libraries in PCB are having good connection with SHELLs. In fact, RC1 from AD is ok. But it's real that the design in RC1 for AD's testing mechanisms is unqualified. After co-working with experienced layout guys here, they do not use this mechanism to complete the layout, because it would allow them to spend more time to process because the AD software too stringent internal testing mechanisms derive the excess of the rectification work. Instead, through PCB and SCH library to do with links, put related PCB manufacturer's capabilities/attributes into the basic parameters of DRC rules is necessary in order to use DRC check action. Usually set Rules more while doing routings, then cancel Rules before generating Gerbers. Well, this time we've learned AD's stringent system. It proves it's powerful. >Apart from these problems and the DRC, it seems OK. Overall, okay; but please comment on 110510 version. Next to generate gerbers/AI files. Thanks a lot. Adam
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