Hi,

Changes summarily again are for Sch/BoM/Route:
http://downloads.qi-hardware.com/hardware/milkymist_one/pcb/rc2/102810/rc2_design.tar.bz2

* Connect P[15:8] instead of P[7:0] on the video decoder chip U21

Changed.

* The installed IR detectors do not work. This is not a PCB problem and it
can be solved by replacing the IR detector module with one from another
source.

To be verified.

* The MIDI optoisolator is not suitable. Replace it with a 6N138S/6N138_X007
and lower R54 to 120 ohms. Connect pin 8 to 3.3V and leave pin 7
unconnected.

Finally used a FAIRCHILD 6N138S with SMDIP-B package.

* For USB to work reliably, 15K pull down resistors must be
installed<http://www.beyondlogic.org/usbnutshell/usb2.htm>on the D+
and D- lines of each USB port (between
the 24 ohm resistors and the
ports<http://www.intel.com/technology/usb/download/usb2dg_r1_0.pdf>).
Add the possibility to make them pull-up resistors to 3.3V (i.e. add
placeholders for pull-ups) so the USB ports could work in device mode with a
small PCB modification.

R166/167, 15K for U16; R168(DNP, 1.5K) --> FULL SPEED; R169(DNP, 1.5K) -->
LOW SPEED;
 R170/171, 15K for U17; R172(DNP, 1.5K) --> FULL SPEED; R173(DNP, 1.5K) -->
LOW SPEED;

* Add 1K pull-down resistor on ETH_RESET_N (specification says reset should
be low during power-up)

R174 added.

* Add 1K pull-down resistor on VIDEOIN_RESET_N (the application schematics
includes external POR circuitry)

R175 added.

* Add notch to mark pin 1 of J3 on silkscreen

Changed, also J5.

* Use red, green and blue connectors for J18

SCP662CNS257U00G<http://downloads.qi-hardware.com/hardware/milkymist_one/datasheet/VideoIn/SCP662CNS257U00G.pdf>
is
now for this.

* We might want a larger soldered area under the pads of U10

To improve this, used several GND via instead of "cross" pad on GND plate to
let heat conducted on both top / bottom GND plate to get good dissipation.
Also changed U13's cross to have a bigger GND plate.

 * Indicate "+/- 5%" and pinout (positive in the middle) near J11 on
silkscreen

Added, but may add an icon of positive dot and negative ring.

* Add a 5V supply pin on the GPIO expansion header

Added.

* Add a test point at the output of the MIDI optoisolator

TP31 Added.

* Add test points on the USB signals (3.3V FPGA side: VP, VM, RCV, OE)

TP22/23/24/25/27/28/29/30 added.

* To reduce audio output noise, power the LM4550 analog supply through an
additional TPS76301 set to 4.3V.

Added part circuits of U23. It's placed near to J12.

* In order to be able to detect board revisions, route 4 FPGA I/O pins to
placeholders for 0402 pull-up resistors. The combination of placed and
non-placed resistors encodes the board revision. The RC2 board should be
encoded as 0001 (ie place only 1 resistor) to distinguish it from RC1 which
does not have any resistor. Use 1K resistors for pull-ups.
R176/177/178/179 are placed in a row on Top.

* Use at least one via for each power or ground pin of the FPGA (i.e. no via
sharing)

Since have added at least one via for most central pins of FPGA, trying to
do instructions below is got a quite unsatisfied results because of via
which are all through holes not blind and buried vias which can place
capacitors on bottom as closer as to center.

* FPGA decoupling: place the 0402 1V2 capacitors closer to the center.
 The larger 0805 capacitors can go further away from the center. For
 example, C53 and C54 should be moved somewhere else and their current
 position taken by 0402 capacitors. Move as many 0402 1V2 capacitors
 as possible under the FPGA and close to the center.

Even though can not implement well above to move all 1V2 capacitors close to
center. RC1 even shares 2 ~ 6 pins on one via on 1V2 power/gnd and got work
well. Yes, it was bad. But the newest RC2 routing gets good power/gnd
driving capability more than RC1 definitely. Right now the capacitors placed
surrounding center area.

* OK not to change the few remaining shared power vias. At least there
 is no via sharing anymore on 1V2 which is where the worst bugs could
 occur.

Same above.

* Add more and bigger decoupling capacitors and more power vias around the
SDRAM
* You do not need to add that many 100uF capacitors on the DRAM. It's
 mostly high frequency noise that we are filtering. Use only one extra
 100uF per chip instead of 4.

Finally added C240/C248/C242/C243/C244/C245/C250/C251/C252. Forgot to delete
C247, will  delete C247.

* Use several vias to connect decoupling capacitors whenever possible,
especially the big ones (>= 10uF)

Modified on each 100uF capactiors.

* I can't find the footprint "SO8-10-2.54" for the optoisolator in
 MilkymistOne.PcbLib - please add it. Also, link the footprint in
 MilkymistOne.SchLib like it's done for other parts.

Added and linked.

* What is the reference document you used for making the optoisolator
 PCB footprint (so I can check it)? Is it the Fairchild datasheet that
 you've linked in the BoM? In this case I need to update the
 milkymist-datasheets repository that contains a datasheet for Vishay
 parts with different footprints.

Used SMDIP-B of http://www.fairchildsemi.com/ds/6N/6N138.pdf
The dimension I checked it 's correct, you can confirm it again.

* Add a 0402 capacitor placeholder between PROGRAM_B and ground to be able
to delay FPGA configuration if needed

C238 on Top.

* Indicate "Not 5V tolerant" near J21 (GPIO expansion header)
Added.

* change the inner diameter of 4 mechanical through holes on board from 3 to
3.2mm.

Done.

* Changed MK1 footprint  to meet part.

* All 0402 footprint changed to be same as
http://en.qi-hardware.com/wiki/File:0603_0402_stencil_aperture_dimension.png


* Other discovery: According to p27 of LM4550B data sheet, R1 is not
required for the LM4550B. Addition of
this resistor will slightly increase the temperature coefficient of the
internal bandgap reference and slightly decrease the THD performance, but
overall performance will still be better than the LM4550. Or ref. to p10 of
http://www.national.com/an/AN/AN-1528.pdf
So I'll DNP R1.

Next steps: fix unsolved items above.

Please comment above.
Thanks,
Adam
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