Hi,
During normal SoC operation, FLASH_RESET_N is pulsed during a system > reset: > > https://github.com/lekernel/milkymist/blob/master/boards/milkymist-one/rtl/system.v#L219 > This allows the flash to operate back properly in read mode to reboot > the system even if the reset occurred during a flash write cycle (which > makes the flash output status information instead of data). > The system.v I don't know it. I drew a manuscript of normal power on and keep a long period then power off sequence: http://en.qi-hardware.com/w/images/e/e3/M1rc2_powerOnOff_sequences_manuscript.jpg Before I wire reset ic's output also connected to this RP# not from FPGA. I monitor when the RP# will activate like said page 17 of http://www.numonyx.com/Documents/Datasheets/319942_J3-65nm_256-Mbit_MLC%20DS.pdf While running Flickernoise, the FLASH_RESET_N doesn't act(goes low) under conditions below: 1, press 'Reboot' button 2, press 'Power off' button it seems that flash read/write status occurs by enabling and disabling OE# & CE# regardless of RP#. Thus the RP# (Reset) is ONLY occurred while M1 power on. If I am right then I can directly cut the route from FPGA then solder it connected to reset ic. Otherwise this cut will become complicated( thus is to add another AND gate for accepting both output from reset ic and fpga then AND gate's output goes to flash RP# pin). Thanks, Adam
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