Hi,
> > 1, press 'Reboot' button > > It is supposed to pulse low at this time. Either you missed the pulse > (it's only a few hundred nanoseconds) or there is a bug somewhere in the > FPGA design. > Used a scope with 1GS/s and 5ns/div to capture it while falling edge at trigger level 3.0V, got nothing. Could you also try to capture it with your scope? > Pressing the 3 buttons at the same time should also reset, again with a > low pulse on FLASH_RESET_N. > True. > > > 2, press 'Power off' button > > The flash does not reset there, this is expected. > > > Thus the RP# (Reset) is ONLY occurred while M1 power on. If I am right > > then I can directly cut the route from FPGA then solder it connected > > to reset ic. > > Please don't - we need the ability to reset the flash from the FPGA in > order to be able to recover from an interrupted write sequence. > Ok. Thanks for clarification. > > To implement then AND, can't we just use a pull-up resistor and the open > drain version of the reset IC connected in parallel on the FPGA pin? > yes, need to try. I used an N-Channel open drain version of the reset ic for PROGRAM_B. Are you saying that also given a reset ic for FLASH_RESET_N individually? Or liked I said in IRC, just pull the PROGRAM_B signal in parallel with FLASH_RESET_N? Before configuration, the FPGA has a weak pull-up on this pin which > would not interfere with the reset IC, and after configuration I can do > whatever I want with this pin. > yes, while monitoring waveforms, I saw this weak too. - Adam
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