On 07/21/2011 10:22 AM, Sebastien Bourdeauducq wrote: > On Thu, 2011-07-21 at 09:42 +0200, Michael Walle wrote: >> ps. imho the irq handling and some cores (like the uart one) needs some >> rework. atm the driver code needs to manually ack the UART irq, which is a >> lm32 arch specific function call (apart from that, the uart driver is >> generic). Additionally, there is no polling possible atm with the UART >> core. > > What about making the IRQs level-sensitive with IP read-only (as > discussed on IRC) and make the "IRQ active" bit visible in each core's > status registers? > >
And IP would be cleared if the interrupted isn't triggered anymore? In my opinion it would be enough if we had the information whether a bit has been received/transmitted was available through a status register. We don't necessarily have to modify the IRQ handling. - Lars _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode Twitter: www.twitter.com/milkymistvj Ideas? http://milkymist.uservoice.com
