On 07/25/2011 09:27 PM, Sebastien Bourdeauducq wrote: > On Mon, 2011-07-25 at 21:18 +0200, Michael Walle wrote: >> - if we want to push lm32 support upstream, we would have to support >> two interrupt controllers in the linux port and qemu. > > Or convince Lattice that level sensitive interrupts are better ;-)
At least for the kernel we could get away with using the same code for both implementations as long as writes to pending are simply ignored by the hardware. >> - although it is duplicating handling, its general practice > > But it's still technically inferior *g* I've actually seen SoCs in the wild which use the proposed scheme. I think we can start with adding IRQ status registers to the device cores. And eventually later make the IRQ controller level sensitive and add auto-ack. - Lars _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode Twitter: www.twitter.com/milkymistvj Ideas? http://milkymist.uservoice.com
