On Thu, 2011-07-21 at 11:00 +0200, Lars-Peter Clausen wrote: > And IP would be cleared if the interrupted isn't triggered anymore?
What we were discussing was moving the interrupt control logic out of the CPU and into the cores. Right now, a core triggers an IRQ by _pulsing_ its interrupt line. The interrupt is registered in LM32, and the bit in IP stays set until IP is written by the software. This has two problems: a) Checking the state of a core needs either reading IP, which is not portable, or duplicating the IRQ information in the core's registers, which is inelegant and a potential source of bugs. b) Some cores like minimac that multiplex several event sources on a single IRQ line need level sensitive lines anyway to avoid race conditions. The proposal is to make LM32's IP stateless, e.g. reading IP yields the instantaneous value of all the (now level sensitive) IRQ lines and writing to it is not possible. The IRQ state is entirely contained in the cores, and can be read and acked using the cores' registers. And indeed, IRQ lines that are deasserted by the cores immediately clear their bits in IP. S. _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode Twitter: www.twitter.com/milkymistvj Ideas? http://milkymist.uservoice.com
