From: Mahadevan P <[email protected]> Nord has a new MDSS 12.1 revision with DPU 1499A and two independent, DP-only display interface controllers (no DSI), which no existing schema describes. Add a dedicated qcom,nord-mdss binding to document.
Assisted-by: LLM Signed-off-by: Mahadevan P <[email protected]> Signed-off-by: Nabige Aala <[email protected]> --- .../bindings/display/msm/qcom,nord-mdss.yaml | 396 +++++++++++++++++++++ 1 file changed, 396 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,nord-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,nord-mdss.yaml new file mode 100644 index 000000000000..abd80dae4e7f --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,nord-mdss.yaml @@ -0,0 +1,396 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,nord-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Nord display subsystem (MDSS) + +maintainers: + - Mahadevan P <[email protected]> + +description: + Nord display subsystem consists of MDSS (display controller), DPU 1499A + (display processing unit), and display interface controllers (DP only, no DSI). + This is MDSS 12.1, DP-only, with 2 independent DP controllers. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,nord-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,nord-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,nord-dp + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,nord-dp-phy + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,nord-dispcc.h> + #include <dt-bindings/clock/qcom,nord-nwgcc.h> + #include <dt-bindings/clock/qcom,nord-tcsrcc.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interconnect/qcom,nord-rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,nord-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&nwgcc NW_GCC_DISP_0_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", "cpu-cfg"; + + interrupts = <GIC_SPI 930 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu_1 0x3e0 0x2>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,nord-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x3000>; + reg-names = "mdp", "vbif"; + + clocks = <&nwgcc NW_GCC_DISP_0_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", "iface", "lut", "core", "vsync"; + + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf4_out: endpoint { + remote-endpoint = <&mdss_dp1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz = /bits/ 64 <417000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz = /bits/ 64 <532000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + + opp-710000000 { + opp-hz = /bits/ 64 <710000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + displayport-controller@af54000 { + compatible = "qcom,nord-dp"; + + reg = <0xaf54000 0x200>, + <0xaf54200 0x200>, + <0xaf55000 0xc00>, + <0xaf56000 0x400>, + <0xaf57000 0x400>, + <0xaf58000 0x400>, + <0xaf59000 0x400>, + <0xaf5a000 0x600>, + <0xaf5b000 0x600>; + + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", "ctrl_link_iface", + "stream_pixel", "stream_1_pixel", + "stream_2_pixel", "stream_3_pixel"; + + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; + assigned-clock-parents = <&dp0_phy 0>, + <&dp0_phy 1>, + <&dp0_phy 1>, + <&dp0_phy 1>, + <&dp0_phy 1>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + phys = <&dp0_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dp0_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + displayport-controller@af5c000 { + compatible = "qcom,nord-dp"; + + reg = <0xaf5c000 0x200>, + <0xaf5c200 0x200>, + <0xaf5d000 0xc00>, + <0xaf5e000 0x400>, + <0xaf5f000 0x400>, + <0xaf60000 0x400>, + <0xaf61000 0x400>, + <0xaf62000 0x600>, + <0xaf63000 0x600>; + + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", "ctrl_link_iface", + "stream_pixel", "stream_1_pixel", + "stream_2_pixel", "stream_3_pixel"; + + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&dp1_phy 0>, + <&dp1_phy 1>, + <&dp1_phy 1>; + + interrupt-parent = <&mdss>; + interrupts = <13>; + + phys = <&dp1_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp1_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp1_in: endpoint { + remote-endpoint = <&dpu_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dp1_out: endpoint { }; + }; + }; + + dp1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dp0_phy: phy@fc3a00 { + compatible = "qcom,nord-dp-phy"; + + reg = <0xfc3a00 0x1d0>, + <0xfc3200 0x128>, + <0xfc3600 0x128>, + <0xfc3000 0x200>; + + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&tcsrcc TCSR_DP_TX_0_CLKREF_EN>; + clock-names = "aux", "cfg_ahb", "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + power-domains = <&rpmhpd RPMHPD_MX>; + }; + + dp1_phy: phy@fc6a00 { + compatible = "qcom,nord-dp-phy"; + + reg = <0xfc6a00 0x200>, + <0xfc6200 0xd0>, + <0xfc6600 0xd0>, + <0xfc6000 0x1c8>; + + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&tcsrcc TCSR_DP_TX_1_CLKREF_EN>; + clock-names = "aux", "cfg_ahb", "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + power-domains = <&rpmhpd RPMHPD_MX>; + }; + }; -- 2.34.1
