Re: [PATCH v2 10/13] phy: qcom: edp: Add Nord spread-spectrum clocking configuration callback

[Abel Vesa]

On 26-10-12 19:02:20, Nabige Aala wrote:
> From: Ritesh Kumar <ritesh.ku...@oss.qualcomm.com>
> 
> Nord requires different SSC register values compared to existing SoCs.
> Add qcom_edp_com_configure_ssc_nord() which programs SSC_PER1/2 with
> fixed values and link-rate-dependent SSC_STEP_SIZE1/2 for RBR, HBR,
> HBR2 and HBR3, per HPG Table 2-9.
> 
> Assisted-by: LLM
> Signed-off-by: Ritesh Kumar <ritesh.ku...@oss.qualcomm.com>
> Signed-off-by: Nabige Aala <nabige.a...@oss.qualcomm.com>
> ---
>  drivers/phy/qualcomm/phy-qcom-edp.c | 36 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c 
> b/drivers/phy/qualcomm/phy-qcom-edp.c
> index c63f721702b1..66c31684c48e 100644
> --- a/drivers/phy/qualcomm/phy-qcom-edp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-edp.c
> @@ -1601,6 +1601,42 @@ static const struct qcom_edp_swing_pre_emph_cfg 
> nord_dp_swing_pre_emph_cfg = {
>       .pre_emphasis_hbr3_hbr2 = &nord_dp_pre_emp_hbr2_hbr3,
>  };
>  
> +static int qcom_edp_com_configure_ssc_nord(const struct qcom_edp *edp)
> +{
> +     const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
> +     u32 step1;
> +     u32 step2;
> +
> +     switch (dp_opts->link_rate) {
> +     case 1620:
> +             step1 = 0x83;
> +             step2 = 0x02;
> +             break;
> +
> +     case 2700:
> +     case 5400:
> +             step1 = 0x18;
> +             step2 = 0x02;
> +             break;
> +
> +     case 8100:
> +             step1 = 0x5b;
> +             step2 = 0x02;
> +             break;
> +
> +     default:
> +             return -EINVAL;
> +     }
> +
> +     writel(0x01, edp->pll + DP_QSERDES_V8_COM_SSC_EN_CENTER);
> +     writel(0x00, edp->pll + DP_QSERDES_V8_COM_SSC_ADJ_PER1);
> +     writel(0x6b, edp->pll + DP_QSERDES_V8_COM_SSC_PER1);
> +     writel(0x02, edp->pll + DP_QSERDES_V8_COM_SSC_PER2);
> +     writel(step1, edp->pll + DP_QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0);
> +     writel(step2, edp->pll + DP_QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0);
> +
> +     return 0;
> +}

Why is this a separate patch?

I think you can squash patches 10 to 13 in a single patch.