Cal Grandy wrote: > Will someone comment on the PC system requirements in regard to Latency > numbers when using FPGA cards such as Mesa 7I43, in a three axis stepper > application? There seems to be so much attention focused on the latency > issuein the EMC documentation etc. The FPGA cards would seem to take much of > the load off the machine processor. > Since you no longer need a base thread at all, the only processing the PC needs to do is at the 1 ms time scale or thereabouts. You can easily tolerate 5-10% timing variation in that thread, so latencies of 50-100us should be fine. Contrast that to 20-30us as a realistic upper bound for reasonable performance with software stepping. For really good software stepping performance, you'd want 10-15us as the upper bound, and the lower the better.
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