On Thu, 25 Mar 2010, Stephen Wille Padnos wrote:
> Date: Thu, 25 Mar 2010 23:47:16 -0400
> From: Stephen Wille Padnos <[email protected]>
> Reply-To: "Enhanced Machine Controller (EMC)"
> <[email protected]>
> To: "Enhanced Machine Controller (EMC)" <[email protected]>
> Subject: Re: [Emc-users] FPGA and Latency
>
> Cal Grandy wrote:
>> Will someone comment on the PC system requirements in regard to Latency
>> numbers when using FPGA cards such as Mesa 7I43, in a three axis stepper
>> application? There seems to be so much attention focused on the latency
>> issuein the EMC documentation etc. The FPGA cards would seem to take much of
>> the load off the machine processor.
>>
> Since you no longer need a base thread at all, the only processing the
> PC needs to do is at the 1 ms time scale or thereabouts. You can easily
> tolerate 5-10% timing variation in that thread, so latencies of 50-100us
> should be fine. Contrast that to 20-30us as a realistic upper bound for
> reasonable performance with software stepping. For really good software
> stepping performance, you'd want 10-15us as the upper bound, and the
> lower the better.
>
> - Steve
>
Also with the rate generator type hardware stepgens (Mesa or Pico USC) an
interesting thing is that even the relaxed 100 usec or so latency is only
critical during fast accell or decell. When you are gliding along at a
constant speed the CPU is hardly needed at all. So even with a crashed CPU
the steps will continue to be generated at the last programmed rate (a good
reason to have watchdog or chargepump shutdown)
Peter Wallace
Mesa Electronics
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