I am not sure I understand this correctly, but maybe this is possible: substract_encoder_offset --> mod_encoder_count --> take_only_needed_MSB --> customized_table_lookup with custom pre-calculated encoder offsets for 120 and 240 degrees --> scale_multiply_sines --> 3_PWMGENS
I mean use pre-calculated sine table for particular encoder scale, possibly shorter by 2, 4, 8, etc. times of encoder counts (rougher) which would be smooth enough. If made open-source, maybe these firmware files could be compiled by the users theirself.. New ideas: Idea #1: use rough sine table in FPGA for fast speed and software for slow speed. Or just give software a possibility to send it's own values, but if it doesn't do that - use hardware's on transition to new table value. Idea #2 (at least): make phase commutation in HW. I mean when sine crosses zero (on hall signal slope), just commutate different phases and leave values the same. On 2013.07.10 16:56, Peter C. Wallace wrote: > Even if just commuation is done in a FPGA its probably a win do use a soft > processor since you need to do mod_encoder_count --> scale multiply --> > table_lookup with 0,120,240 deg offsets --> scale multiply sines --> 3_PWMGENS > for each channel... ------------------------------------------------------------------------------ See everything from the browser to the database with AppDynamics Get end-to-end visibility with application monitoring from AppDynamics Isolate bottlenecks and diagnose root cause in seconds. Start your free trial of AppDynamics Pro today! http://pubads.g.doubleclick.net/gampad/clk?id=48808831&iu=/4140/ostg.clktrk _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
