Can you help me with the following questions:
Bus Master IDE rev 1.0
- When the start bit is cleared and ACTIVE bit in the Bus Master IDE
status register is set -
What is the correct behavior of the DMA? Let's assume
that a command using UDMA protocol is ongoing:
Abort the ATA command? How? Perform burst termination?
OR
Waits till command completion?
Queued DMA commands
- Are there any working solutions with these commands? Can I rely on
it's stability?
- Can the host check the status of the queued commands within the device?
Does the device provide an indication when it's
queue is full? or
Must the host controller count the commands getting
in/out from the device's queue?
- The queue depth supported by the device is indicated in word
75 of the IDENTIFY DEVICE response.
What is the possible values? anything goes
in a range of 1 to 32? or only a power of two (1,2,4,8,16,32)?
Thanks in advance,
Yaniv Shapira
Tel: 972-8-9247555/1318
Email: [EMAIL PROTECTED]
Galileo Technology Ltd. - A Marvell company
