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Looks like a timing issue just waiting to occur to me.  

clearing status bits while setting others....hmmmm, I seem to remember some old 
old issues concerning this sort of behaviour and adding little time delays 
before checking status registers.....IMO.

gary


> 
> From: [EMAIL PROTECTED]
> Date: 2004/11/15 Mon AM 11:48:40 EST
> To: [EMAIL PROTECTED]
> Subject: [t13] e04155r0 - DRQ=0 When ERR=1 Feature
> 
> This message is from the T13 list server.
> 
> 
> 
> 
> 
> 
> I have some questions about the new proposal
>       "e04155r0 - DRQ=0 When ERR=1 Feature and Allocation Identify Device
> Words Proposal"
>       http://t13.org/docs2004/e041559r0-DRQ-ERR-and-ID-Words.pdf
> 
> Why do we need this ?
> What problem does it really solve ?
> Why should we define a feature that allows a BAD DEVICE to do something
> stupid
>       instead of fixing the bad device ?
> 
> Thank You !!
> -----------------------------------------------------------------
> Jim Hatfield
> ATA Interface Firmware & T13 (ATA/ATAPI) Standards Representative
> Seagate Technology LLC
>    e-mail:  [EMAIL PROTECTED]
>    s-mail:  389 Disc Drive;  Longmont, CO 80503 USA
>    voice:  720-684-2120
>    fax....:  720-684-2711
> ====================================================
> 
> 

gary laatsch
[EMAIL PROTECTED]

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