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[[[Sorry my mailer sent a duplicate of this to GL already.]]]
Example: is it is virtually impossible to clear DRQ at exactly the same time that ERR is set. Hence there will always be some sort of overlap where the state is undefined (DRQ -> 0 whiles ERR -> 1). That is the window I am concerned about.
Yes, it's difficult to avoid seeing a spurious b11 or b00 in the change between b01 and b10: that's why Gray codes exist. But to avoid DRQ and ERR appearing together, we should be asking the device to clear both or either before clearing BSY. That's something device hardware - though maybe not device firmware - actually can easily choose to do.
Pat LaVarre
P.S. How exactly ATA and ATAPI device hardware folk arrange for BSY DRQ to cycle always thru b 00 10 11 01 11 10 00 and make b11 rare and never spuriously produce a b00 in the middle, I've never entirely understood. Any ASIC folk want to comment? Seems like double-latching to synchronise clocks would open a b11 window wide ...
