I'd like to report an issue I've seen related to the ATA specification (PACKET command protocol in ATA-7, volume 2). The issues shows up on an Plextor PX-716SA (SATA), ASUS A8N-SLI Deluxe, AMD3800.
Problem:
On transition from HP4 to HP2, host waits one PIO cycle (via reading alternate status), then reads the status register.
The status register is still 58h. (device has not transitioned to DP2 yet and host thinks it's ready for next DRQ data block).
This only occurs on writing so it suggests the device isn't ready for more IO.
Suggestion Solution (Tighten the spec):
Regardless of nIEN, the device must transition from DP4 to DP2 (set busy) within one PIO cycle. It can then wait with BSY set until ready for next DRQ block.
In general a device shouldn't rely on nIEN to determine the order of when it sets/clears bits since in some shared environments modifying nIEN can cause problems and PIO should work regardless.
--
David F.
TeraByte Unlimited
http://www.terabyteunlimited.com
