This message is from the T13 list server.
> -----Original Message----- > From: Hale Landis [mailto:[EMAIL PROTECTED] > Sent: Wednesday, June 08, 2005 2:39 PM > To: David F. > Cc: 'T13 List Server' > Subject: Re: [t13] PACKET command protocol issue. > > David F. wrote: > > This message is from the T13 list server. > > 4 PIO cycles, 400ns, 1 PIO cycle - doesn't matter to me, > only that the > > spec is tightened and reliable. > > I don't think the spec for setting switching from BSY=0 DRQ=1 > to BSY=1 status could be more clear... In ATA/ATAPI-7, clause > "5.14.5.5 DRQ (Data request)", see the statment "The DRQ bit > shall be cleared to zero by the > device: 1) when the last word of the data transfer occurs; > ...". This rule has always been interpreted to mean that the > device switches from BSY=0 DRQ=1 to BSY=1 or to BSY=0 DRQ=0 > during the transfer of the last word of a DRQ data block. And > most devices are implemented this way - even most ATAPI > devices. On the host side there was a requirement for the > host to wait 400ns (now one read of Alt Status, maybe 100ns) > before reading and using the device status. I must say that > for PATA devices, both ATA and ATAPI I don't think I've ever > seen a failure to make this switch BSY=0 DRQ=1 to BSY=0 > status within even 100ns. > > I don't think this is a spec issue. It could be an nIEN=1 > problem with a SATA host controller or SATA device (see my > other email). Thanks! Yes, I had recalled seeing that (but didn't recall where it was - and that's part of the problem). Perhaps it's just an issue that the PROTOCOL section needs to be updated to reflect the rules (cross ref 5.14.5.5 or duplicate) because this problem has showed up in at least this one device. Perhaps they only looked at the Protocol section (which seems to me, should be the actual detailed Protocol to use - kept in one place.). Still, just a suggestion.
