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<snip> > > Suggestion Solution (Tighten the spec): > > Regardless of nIEN, the device must transition from DP4 to DP2 (set > > busy) within one PIO cycle. It can then wait with BSY set > until ready > > for next DRQ block. > > I disagree... To correct fix is to change the spec back to 400ns... > There is rarely a problem with ATAPI devices if the host follows the > ATA/ATAPI-4 or -5 spec of 400ns for this delay. > 4 PIO cycles, 400ns, 1 PIO cycle - doesn't matter to me, only that the spec is tightened and reliable. It takes between 0-35 PIO cycles for BSY to set and DRQ to clear when WRITING .. Suggesting that they are not transitioning until the device is ready for the next DRQ block. They should be setting BSY/clearing DRQ within the (missing) spec and wait with BSY set until the device can receive the next DRQ block. > > In general a device shouldn't rely on nIEN to determine the > order of > > when it sets/clears bits since in some shared environments > modifying > > nIEN can cause problems and PIO should work regardless. > > I'm not sure what you are saying... A PATA device asserts > INTRQ _after_ it has changed its status from BSY=1 to BSY=0 > (except in a few specific cases when INTRQ is not used at all > when BSY changes from 1 to 0, ie, resets and the first DRQ > block for PIO Data Out commands). > Some devices assume they can be sloppy with setting status bits / transitioning when nIEN==0.
