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David F. wrote:
I'd like to report an issue I've seen related to the ATA specification (PACKET command protocol in ATA-7, volume 2). The issues shows up on an Plextor PX-716SA (SATA), ASUS A8N-SLI Deluxe, AMD3800. Problem: On transition from HP4 to HP2, host waits one PIO cycle (via reading alternate status), then reads the status register.
This host delay used to be specified as 400ns or approximately 4 reads of the Alt Status ignoring the data received. I can not find when or why this was changed to 1 read. Can anyone find the proposal and or meeting mintues when this change was proposal and accepted? I'm thinking this is yet another error that was introduced into ATA/ATAPI-7 when SATA was added. ATA/ATAPI-7 has many of these problems - things that will probably work with SATA but break traditional PATA implementations. This is one of my reasons for saying that ATA/ATAPI-7 should never be published - at least not until these problems are fixed or T13 gives up and admits that ATA/ATAPI-6 is the last valid document for PATA and that SATA is defined by the SATA secret society.
The status register is still 58h. (device has not transitioned to DP2 yet and host thinks it's ready for next DRQ data block).
Certainly there are some slow devices out there. My guess is the drive your are using would not fail if your host waited the 400ns as spec'ed by ATA/ATAPI-4 and -5. Remember these things when working with ATAPI devices, especially CD/DVD devices: 1) Most are still implemented per the very obsolete SFF-8020 spec, 2) most of these device implementors have never read any ATA/ATAPI-x document, 3) even devices that claim ATA/ATAPI-4 compliance rarely work correctly. To this day many ATAPI CD/DVD devices will not work correctly unless you delay 50ms to 100ms whenever the device is expected to change from BSY=1 to BSY=0 status - and especially if the host is polling and not using interrupts.
Suggestion Solution (Tighten the spec): Regardless of nIEN, the device must transition from DP4 to DP2 (set busy) within one PIO cycle. It can then wait with BSY set until ready for next DRQ block.
I disagree... To correct fix is to change the spec back to 400ns... There is rarely a problem with ATAPI devices if the host follows the ATA/ATAPI-4 or -5 spec of 400ns for this delay.
In general a device shouldn't rely on nIEN to determine the order of when it sets/clears bits since in some shared environments modifying nIEN can cause problems and PIO should work regardless.
I'm not sure what you are saying... A PATA device asserts INTRQ _after_ it has changed its status from BSY=1 to BSY=0 (except in a few specific cases when INTRQ is not used at all when BSY changes from 1 to 0, ie, resets and the first DRQ block for PIO Data Out commands).
Hale -- ++ Hale Landis ++ www.ata-atapi.com ++
