> Hello Bruce,
> I have also created dual foot print SMT/thru hole components. The work
> around that I use (and it is not a good one) is to manually assign the
> proper nets to the copper after bring it into the PCB. You may also be
able
> to use "Update Free Primitives From Component Pads" from "Netlist
Manager".
> I have never tried this method. I hope that this helps.....
>
> John Branthoover
Each of two different PCBs that I am currently designing can be fitted with
either a through-hole (DPDT) relay or a SM (DPDT) relay, and the footprints
for each of these partially overlap. (A SM relay will be fitted by
preference, but in the event of supply problems, a through-hole relay can be
fitted instead.)
I have designated the SM relay as REL1 and the through-hole relay as REL1A;
the Designator string for the latter has been concealed. As such, it gives
the impression that "REL1" can be either a SM or through-hole relay.
I have *also* done a similar thing on each (PCB's corresponding) *schematic*
file; the *same* component has been added to each such file *twice*. Again,
one of these has a designator of REL1 (and its footprint has been set to the
SM footprint), while the other has a (concealed) designator of REL1A (and
its footprint has been set to the through-hole footprint). And I have placed
*both* of these components in (exactly) the *same* location, so it looks as
though (and prints out as) there is only one relay in the schematic file (to
wit, "REL1"). (Given that only one relay can be fitted on each actual PCB
(due to the overlapping footprints), the above technique is not totally
mis-leading, and I have added a note to each schematic file which specifies
that either a SM or through-hole relay can be fitted for REL1. And the list
of components, and any BOM file produced from each schematic file, lists
both REL1 and REL1A, while dots on each pin connected to a wire indicates
that it is not a wire connecting to just one pin, but a wire connecting to
*more* than one pin.)
This technique may not *always* be applicable, but it can be useful in
scenarios where multiple footprints are supported (e.g. a through-hole
capacitor or SM capacitor, etc). The advantage of this approach is that the
netlist file created from each schematic file can be loaded in to the PCB
file without any modifications, and no modifications need to be made to the
PCB file (netwise) after the netlist file has been loaded into this.
(There is a "nuisance factor" in that otherwise unused pins within each
device will have a net produced which stipulates that the corresponding pins
within each footprint be routed to one another. It probably would be
possible to figure out some way to deal with this, but I have not done so to
date. I either route the connections concerned, or purge the nets from the
PCB file (so the lack of connections between the pads concerned is not
reported as a DRC error). But in spite of this consideration, I still think
that the above technique has much to be said for it, or at least in many
situations (including situations where *all* of the pins are connected to
something else, so preventing this "nuisance factor" from being a
drawback).)
Regards,
Geoff Harland.
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