Narvi wrote:
> Speculative writes can only happen to pages in the TLB (so you don't get
> speculative TLB misses and replacements), not having a large amount of 4M
> pages around in the TLB means that addresses covered by these can't
> possibly be involved in speculative writes.
> I personaly suspect the reason the cache line flushes of speculatively
> "written to" cache lines derive from the AMD-s use of MOESI coherency and
> mapping that to actual bits. Another "minor" side effect is that you get
> direct cache-to-cahce transfers in SMP systems for shared data.

I think that the problem is more related to the fact that
there are 16 TLB entries for 4K data pages, 16 for 4K code
pages, and another 8 for 4M pages.

Peter is right, in other words, because there is a problem
with the interaction of 4K and 4M pages.  I've seen this
myself, as I've previously reported, as well as seeing other
problems (and knowing how to work around them, after weeks
of investigation into characterizing them).

Note that I was "lucky", in that I had modified the FreeBSD
kernel to use certain types of mappings in a certain way;
I think it would be very difficult, or impossible, for
anyone else to duplicate the problem in order to better
characterize it beyond "DISABLE_PSE", except the chip
vendors themselves, if they started from first principles
with a simulation.

-- Terry

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