On 4/7/2018 5:51 PM, Dana Myers wrote:
Now I want to hunt down the appropriate Tensilica reference for the core in the ESP32; it occurs to me the two cores may be sharing one FPU, though I don't immediately see how the simple test would incur context switching frequently.
The Xtensa LX6 core is highly configurable - it's not clear to me that Espressif actually included the FPU hardware in ESP32 SoC, but boiler- plated the Xtensa LX6 datasheet into their own. Given the times observed in the blog post, I think it's soft FPU emulation. Single-precision addition was 8.7uS at 240MHz; I think that's ~2100 clock cycles. Single-precision multiplication was around 1000 clocks. That's not a slow FPU IMO, that's software emulation. 73, Dana K6JQ ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ Freetel-codec2 mailing list Freetel-codec2@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/freetel-codec2
