On 4/7/2018 5:22 PM, Bruce Perens wrote:
It could also be the use of memory barrier instructions. I'd like to benchmark Codec2 rather than a simple floating point loop with volatile variables. But if we are to believe the times on the screen of the esp32 in the video, he was getting acceptable performance.

From what I've seen, the Cortex-M FPUs basically give single-precision
FP add/sub/mul in the same number of clocks as integer operations.

With a proper program store cache, Cortex-M4F is quite the rocket, really.

Now I want to hunt down the appropriate Tensilica reference for the core
in the ESP32; it occurs to me the two cores may be sharing one FPU,
though I don't immediately see how the simple test would incur context
switching frequently.

73,
Dana  K6JQ


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